JPH048450U - - Google Patents
Info
- Publication number
- JPH048450U JPH048450U JP1990047887U JP4788790U JPH048450U JP H048450 U JPH048450 U JP H048450U JP 1990047887 U JP1990047887 U JP 1990047887U JP 4788790 U JP4788790 U JP 4788790U JP H048450 U JPH048450 U JP H048450U
- Authority
- JP
- Japan
- Prior art keywords
- mos
- zener diode
- electrode
- fet
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
第１図は本考案の一実施例を示すものであつて
、同図イはツエナーダイオード付きＭＯＳ−ＦＥ
Ｔの構成を示す縦断面図、同図ロはツエナーダイ
オード付きＭＯＳ−ＦＥＴの半導体ペレツトをリ
ードフレームに実装したときの平面図、同図ハは
ツエナーダイオード付きＭＯＳ−ＦＥＴの回路図
である。第２図はＭＯＳ−ＦＥＴの基本構成を説
明するためのものであつて、同図イはＭＯＳ−Ｆ
ＥＴの構成を示す縦断面図、同図ロはＭＯＳ−Ｆ
ＥＴの回路図である。第３図は従来のツエナーダ
イオード付きＭＯＳ−ＦＥＴを示すものであつて
、同図イはツエナーダイオード付きＭＯＳ−ＦＥ
Ｔの構成を示す縦断面図、同図ロはツエナーダイ
オード付きＭＯＳ−ＦＥＴの半導体ペレツトをリ
ードフレームに実装したときの平面図、同図ハは
ツエナーダイオード付きＭＯＳ−ＦＥＴの回路図
である。
１……半導体基板、２……ゲート酸化膜、３…
…ゲート電極、６……カソード電極（ツエナーダ
イオードの電極）、１６，１８……ボンデイング
ワイヤ。
FIG. 1 shows an embodiment of the present invention, in which A is a MOS-FE with a Zener diode.
FIG. 2B is a longitudinal cross-sectional view showing the structure of T, FIG. Figure 2 is for explaining the basic configuration of MOS-FET, and figure A is MOS-FET.
A vertical cross-sectional view showing the configuration of ET.
It is a circuit diagram of ET. Figure 3 shows a conventional MOS-FET with a Zener diode, and Figure A shows a MOS-FE with a Zener diode.
FIG. 2B is a longitudinal cross-sectional view showing the structure of T, FIG. 1... Semiconductor substrate, 2... Gate oxide film, 3...
... Gate electrode, 6 ... Cathode electrode (electrode of Zener diode), 16, 18 ... Bonding wire.
Claims (1)
ＥＴのゲート酸化膜を絶縁破壊から保護するため
のツエナーダイオードとが形成された半導体装置
において、 半導体基板上でＭＯＳ−ＦＥＴのゲート電極と
ツエナーダイオードの電極とが分離して形成され
ると共に、このゲート電極とツエナーダイオード
の電極とがボンデイングワイヤを介して接続され
たことを特徴とする半導体装置。[Scope of claim for utility model registration] MOS-FET and this MOS-F on a semiconductor substrate
In a semiconductor device in which a Zener diode is formed to protect the gate oxide film of the ET from dielectric breakdown, the gate electrode of the MOS-FET and the electrode of the Zener diode are formed separately on the semiconductor substrate, and this A semiconductor device characterized in that a gate electrode and an electrode of a Zener diode are connected via a bonding wire.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990047887U JPH048450U (en) | 1990-05-07 | 1990-05-07 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990047887U JPH048450U (en) | 1990-05-07 | 1990-05-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH048450U true JPH048450U (en) | 1992-01-27 |
Family
ID=31564214
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1990047887U Pending JPH048450U (en) | 1990-05-07 | 1990-05-07 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH048450U (en) |
-
1990
- 1990-05-07 JP JP1990047887U patent/JPH048450U/ja active Pending
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