JPH0484782A - Test circuit - Google Patents

Test circuit

Info

Publication number
JPH0484782A
JPH0484782A JP2199560A JP19956090A JPH0484782A JP H0484782 A JPH0484782 A JP H0484782A JP 2199560 A JP2199560 A JP 2199560A JP 19956090 A JP19956090 A JP 19956090A JP H0484782 A JPH0484782 A JP H0484782A
Authority
JP
Japan
Prior art keywords
signal
output
lsi
test mode
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2199560A
Other languages
Japanese (ja)
Inventor
Osamu Yoshida
修 吉田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2199560A priority Critical patent/JPH0484782A/en
Publication of JPH0484782A publication Critical patent/JPH0484782A/en
Pending legal-status Critical Current

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  • Tests Of Electronic Circuits (AREA)

Abstract

PURPOSE:To enable testing with a simple circuit and without increasing LSI terminals by providing an output circuit to output LSI interval signal to the outside of LSI, and a comparator circuit to compare the LSI internal signal and the LSI external signal. CONSTITUTION:A test circuit has an output circuit (inverter) 1 and a comparator circuit consisting of an inverter 2 and an EXOR 3. When a logic signal is input to a data line 5 to output to an outside terminal 4, the reversed signal is output to the terminal. As an equal logic level is always input to the 2 side of the EXOR 3 at this time, its output, a test mode signal 6 is always in low level and in the non-test mode state. To make it in the test mode, the logic level of the output from the terminal 4 is measured and its reversed signal is forced to input and then the signal 6 becomes high level to be in the test mode state. And when the forced input to the terminal 4 is released, the test mode is released.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はテスト回路に関し、特にＬＳＩのテスト回路に
関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a test circuit, and particularly to an LSI test circuit.

〔従来の技術〕[Conventional technology]

従来、この種のテスト回路は第２図に示すようにテスト
モード専用端子を複数個ＬＳＩに設けて、各テストモー
ドに設定しテストする方法が一般的である。Conventionally, in this type of test circuit, as shown in FIG. 2, a common method is to provide a plurality of test mode dedicated terminals on an LSI and set each test mode for testing.

また、リセット端子（たいていのＬＳＩには存在する端
子）を利用し、電源端子に通常印加される電圧（例とし
て０〜５Ｖ）より高い電圧（例とし電源端子に印加され
る電圧の２倍程度）をリセット端子に印加する事でテス
トモードに設定する方法もある。In addition, by using a reset terminal (a terminal that exists in most LSIs), a voltage higher than the voltage normally applied to the power supply terminal (for example, 0 to 5V) (for example, about twice the voltage applied to the power supply terminal) can be used. ) is also applied to the reset pin to set the test mode.

サラに、マイクロコンピュータ等では、リセット端子に
よるリセット解除後、ＬＳＩ内部テストプログラムが作
動し通常ありえないと判断できるタイミングで各端子（
各ポート）にデータを入力するとテストモードに設定で
きる方法もある。Generally speaking, in microcomputers, etc., after the reset is canceled by the reset terminal, the LSI internal test program is activated and each terminal (
There is also a method that allows you to enter test mode by inputting data to each port.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

この従来のテスト回路では、テスト用端子が複数必要で
あるため小数ピンのＬＳＩには適用するのが困難であっ
たり、回路規模が大きくテストモードに設定するのが複
雑である。Since this conventional test circuit requires a plurality of test terminals, it is difficult to apply it to an LSI with a small number of pins, and the circuit scale is large, making it complicated to set it in a test mode.

〔課題を解決するための手段〕[Means to solve the problem]

本発明のテスト回路は、ＬＳＩ内部信号をＬＳＩ外部へ
出力する出力回路と、ＬＳＩ内部信号とＬＳＩ外部信号
を比較する比較回路とを備えている。The test circuit of the present invention includes an output circuit that outputs an LSI internal signal to the outside of the LSI, and a comparison circuit that compares the LSI internal signal and the LSI external signal.

〔実旅例〕[Actual travel example]

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第１図は本発明の一実施例のテスト回路である。FIG. 1 shows a test circuit according to an embodiment of the present invention.

このテスト回路は、出力回路（インバータ）１およびイ
ンバータ２とＥＸＯＲ３で構成された比較回路を有する
。また、４は外部端子、５は外部端子４に圧力するデー
タ線、６はテストモード信号である。This test circuit has an output circuit (inverter) 1 and a comparison circuit composed of an inverter 2 and an EXOR 3. Further, 4 is an external terminal, 5 is a data line that applies pressure to the external terminal 4, and 6 is a test mode signal.

次に動作を説明すると、５に論理信号を入力するとその
反転信号が４に出力される。（出力ポート動作）この時
、ＥＸＯＲの２人力には常に同−論理レベルが入力され
るため、その出力であるテストモード信号６は常にロウ
レベルであり、非テストモード状態になっている。ここ
で、テストモードにするには、４の圧力の論理レベルを
測定し、その反転信号を強制的に入力すると、テストモ
ード信号６はハイレベルとなりテストモード状態に入る
。また４の強制入力を解除すれば、テストモードが解除
される。Next, the operation will be explained. When a logic signal is input to 5, its inverted signal is output to 4. (Output port operation) At this time, since the same logic level is always input to the two EXORs, the test mode signal 6 which is the output thereof is always at a low level, and is in a non-test mode state. To enter the test mode, measure the logic level of the pressure 4 and forcibly input the inverted signal, the test mode signal 6 becomes high level and enters the test mode state. Moreover, if the forced input in step 4 is canceled, the test mode is canceled.

第３図は、前述実施例の比較回路を論理レベルからアナ
ログレベルに変更した第２の実施例である。これは、通
常動作時（非テストモード）に外部端子１４にＬＥＤ　
（発光ダイオード）が付加されている場合などは流れる
電流により論理レベルが反転して見える事がありえる（
テストモードに入ってしまう）ため、そのしきい値電圧
をＣＭＯＳレベルではなく、電源電圧側もしくはクラン
ド側にずらす必要があるためである。FIG. 3 shows a second embodiment in which the comparison circuit of the previous embodiment is changed from a logic level to an analog level. This indicates that the LED is connected to external terminal 14 during normal operation (non-test mode).
(If a light emitting diode) is added, the logic level may appear to be reversed due to the flowing current (
This is because it is necessary to shift the threshold voltage not to the CMOS level but to the power supply voltage side or ground side.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、ＬＳＩの出力回路に比較
回路を追加する事により、ＬＳＩの端子を増やす事なく
かつ簡単な回路にてテスト回路を構成できるという効果
を有する。As explained above, the present invention has the effect that by adding a comparison circuit to the output circuit of an LSI, a test circuit can be configured with a simple circuit without increasing the number of terminals of the LSI.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例の回路図、第２図は従来例の
ブロック図、第３図は本発明の第２の実施例である。 １．２．１１・・・・・・インバータ、３．１３・・・
・・・ＥＸＯＲ，４，７，８，９，１４・・・・・・Ｌ
ＳＩ外部端子、５，１５・・・・・・ＬＳＩデータ線、
６，１６・・・・・・テストモード信号、１０・・・・
・・ＬＳＩ、１２・・・・・・コンパレータ、１７．１
８・・・・・・比較用抵抗。FIG. 1 is a circuit diagram of one embodiment of the present invention, FIG. 2 is a block diagram of a conventional example, and FIG. 3 is a second embodiment of the present invention. 1.2.11... Inverter, 3.13...
...EXOR, 4, 7, 8, 9, 14...L
SI external terminal, 5, 15... LSI data line,
6, 16...Test mode signal, 10...
...LSI, 12...Comparator, 17.1
8...Resistance for comparison.

Claims (1)

【特許請求の範囲】[Claims] 複数の出力回路と複数の比較回路を備えた事を特徴とす
るテスト回路。A test circuit characterized by having multiple output circuits and multiple comparison circuits.
JP2199560A 1990-07-27 1990-07-27 Test circuit Pending JPH0484782A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2199560A JPH0484782A (en) 1990-07-27 1990-07-27 Test circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2199560A JPH0484782A (en) 1990-07-27 1990-07-27 Test circuit

Publications (1)

Publication Number Publication Date
JPH0484782A true JPH0484782A (en) 1992-03-18

Family

ID=16409859

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2199560A Pending JPH0484782A (en) 1990-07-27 1990-07-27 Test circuit

Country Status (1)

Country Link
JP (1) JPH0484782A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018036253A (en) * 2016-08-26 2018-03-08 エイブリック株式会社 Semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55149063A (en) * 1979-04-27 1980-11-20 Philips Nv Integrated circuit testing method and apparatus
JPS6180068A (en) * 1984-09-28 1986-04-23 Nec Corp Test signal generation circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55149063A (en) * 1979-04-27 1980-11-20 Philips Nv Integrated circuit testing method and apparatus
JPS6180068A (en) * 1984-09-28 1986-04-23 Nec Corp Test signal generation circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018036253A (en) * 2016-08-26 2018-03-08 エイブリック株式会社 Semiconductor device

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