JPH0485730U

JPH0485730U -

Info

Publication number: JPH0485730U
Application number: JP12875490U
Authority: JP
Priority date: 1990-11-29
Filing date: 1990-11-29
Publication date: 1992-07-24

Description

[Brief explanation of drawings]

第１図は本考案の実施例１の概略図（ブロツク
図）、第２図は実施例１における干渉性膜の膜厚
とセンサヘツドの受光するウエハーより反射した
光の反射強度との関係のグラフ、第３図および第
４図は実施例２における概略図および膜厚と反射
強度の関係のグラフ、第５図はウエハーの裏面に
まわり込み成膜をした干渉性膜の図、第６図は単
一の反射型センサを用いた場合の膜厚に対する反
射強度の関係図で、第７図は検知装置の概略図、
第８図は第７図のウエハー検知装置部のセンサヘ
ツド部分の拡大図である。１……ウエハー、２，３，４……センサヘツド
、５，６，７……センサ電源、８……ＯＲ論理回
路、９……ＣＰＵＩ／Ｏボード、１０……第１
センサヘツドの受光した干渉波形、１１……第２
センサヘツドの受光した干渉波形、１２，１３…
…センサ不感膜厚領域、１４……センサ不感領域
、１５……第３センサヘツドの受光した干渉波形
、１０１……発光路、１０２……反射光路。 Fig. 1 is a schematic diagram (block diagram) of Embodiment 1 of the present invention, and Fig. 2 is a graph of the relationship between the thickness of the coherent film and the reflection intensity of the light reflected from the wafer received by the sensor head in Embodiment 1. , FIGS. 3 and 4 are schematic diagrams and graphs of the relationship between film thickness and reflection intensity in Example 2, FIG. 5 is a diagram of the coherent film formed around the back surface of the wafer, and FIG. This is a diagram showing the relationship between reflection intensity and film thickness when a single reflection sensor is used. Figure 7 is a schematic diagram of the detection device;
FIG. 8 is an enlarged view of the sensor head portion of the wafer detection device section of FIG. 7. 1... Wafer, 2, 3, 4... Sensor head, 5, 6, 7... Sensor power supply, 8... OR logic circuit, 9... CPU I/O board, 10... First
Interference waveform received by the sensor head, 11...2nd
Interference waveforms received by the sensor head, 12, 13...
...Sensor insensitive film thickness area, 14...Sensor insensitive area, 15...Interference waveform received by the third sensor head, 101...Emission path, 102...Reflection optical path.

Claims

[Scope of utility model registration request]

multiple sensor heads that emit light at different wavelengths;
A wafer detection device having a plurality of sensor power supplies that input the outputs of the plurality of sensor heads and output a wafer presence/absence signal, and a logic circuit that inputs the outputs of the plurality of sensor power supplies and outputs their logical sum. .