JPH0485924U - - Google Patents

Info

Publication number
JPH0485924U
JPH0485924U JP12731190U JP12731190U JPH0485924U JP H0485924 U JPH0485924 U JP H0485924U JP 12731190 U JP12731190 U JP 12731190U JP 12731190 U JP12731190 U JP 12731190U JP H0485924 U JPH0485924 U JP H0485924U
Authority
JP
Japan
Prior art keywords
signal
filter
output
gate
latch means
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12731190U
Other languages
Japanese (ja)
Other versions
JPH0810978Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP12731190U priority Critical patent/JPH0810978Y2/en
Publication of JPH0485924U publication Critical patent/JPH0485924U/ja
Application granted granted Critical
Publication of JPH0810978Y2 publication Critical patent/JPH0810978Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Manipulation Of Pulses (AREA)
  • Logic Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例を示す構成ブロツク
図、第2図は第1図回路の動作を示すタイムチヤ
ート、第3図は従来回路の一例を示すブロツク図
、第4図はその動作を示すタイムチヤートである
。 1……フイルタ、2……ゲート、3……ラツチ
手段、4……リセツト信号出力手段、5……オア
ゲート。
Fig. 1 is a configuration block diagram showing an embodiment of the present invention, Fig. 2 is a time chart showing the operation of the circuit shown in Fig. 1, Fig. 3 is a block diagram showing an example of a conventional circuit, and Fig. 4 is its operation. This is a time chart showing. 1... Filter, 2... Gate, 3... Latch means, 4... Reset signal output means, 5... OR gate.

Claims (1)

【実用新案登録請求の範囲】 入力信号の中に含まれる単発パルスを除去する
フイルタ1と、このフイルタからの信号を所定の
スキヤン周期で印加される読込み信号により読込
むためのゲート2とを備えたステータス信号読込
み回路において、 前記フイルタ1からの信号を入力し、その立ち
上がりまたは立ち下がりをラツチするラツチ手段
3と 前記スキヤン周期で印加される読込み信号を入
力し、当該読込み信号に遅れたタイミングで同期
するリセツト信号を前記ラツチ手段3のリセツト
端子に出力するリセツト信号出力手段4と、 フイルタの出力と前記ラツチ手段からの出力と
を入力しその出力を前記ゲート2に印加させるオ
アゲート5と を設けたことを特徴とするステータス信号読込み
回路。
[Claims for Utility Model Registration] A status device comprising a filter 1 for removing a single pulse contained in an input signal, and a gate 2 for reading a signal from this filter using a read signal applied at a predetermined scan period. In the signal reading circuit, a latch means 3 which inputs the signal from the filter 1 and latches the rise or fall of the signal, and a latching means 3 which inputs the read signal applied in the scan period and synchronizes at a timing delayed with the read signal. A reset signal output means 4 for outputting a reset signal to the reset terminal of the latch means 3, and an OR gate 5 for inputting the output of the filter and the output from the latch means and applying the output to the gate 2. A status signal reading circuit featuring:
JP12731190U 1990-11-29 1990-11-29 Status signal reading circuit Expired - Lifetime JPH0810978Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12731190U JPH0810978Y2 (en) 1990-11-29 1990-11-29 Status signal reading circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12731190U JPH0810978Y2 (en) 1990-11-29 1990-11-29 Status signal reading circuit

Publications (2)

Publication Number Publication Date
JPH0485924U true JPH0485924U (en) 1992-07-27
JPH0810978Y2 JPH0810978Y2 (en) 1996-03-29

Family

ID=31874812

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12731190U Expired - Lifetime JPH0810978Y2 (en) 1990-11-29 1990-11-29 Status signal reading circuit

Country Status (1)

Country Link
JP (1) JPH0810978Y2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018063691A (en) * 2016-10-14 2018-04-19 エルエス産電株式会社Lsis Co., Ltd. Apparatus for recognizing a pulse signal

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018063691A (en) * 2016-10-14 2018-04-19 エルエス産電株式会社Lsis Co., Ltd. Apparatus for recognizing a pulse signal
CN107959484A (en) * 2016-10-14 2018-04-24 Ls 产电株式会社 Equipment for identifying pulse signal
US10110236B2 (en) 2016-10-14 2018-10-23 Lsis Co., Ltd. Apparatus for recognizing pulse signal

Also Published As

Publication number Publication date
JPH0810978Y2 (en) 1996-03-29

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Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term