JPS5963739U - Digital signal input device - Google Patents
Digital signal input deviceInfo
- Publication number
- JPS5963739U JPS5963739U JP15620182U JP15620182U JPS5963739U JP S5963739 U JPS5963739 U JP S5963739U JP 15620182 U JP15620182 U JP 15620182U JP 15620182 U JP15620182 U JP 15620182U JP S5963739 U JPS5963739 U JP S5963739U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- capture
- latch
- gate
- clock pulse
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Information Transfer Systems (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案の一実施例を示すブロック図、第２図は
第１図の動作例を示すタイムチャートである。
１ １・・・クロックパルス発生回路、２・・・ゲート
、３．４・・・ラッチ、５・・・信号変化検出回路、６
・・・制御回路、７・・・操作部、８・・・信号処理回
路。FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a time chart showing an example of the operation of FIG. 1 1... Clock pulse generation circuit, 2... Gate, 3.4... Latch, 5... Signal change detection circuit, 6
. . . control circuit, 7 . . . operation unit, 8 . . . signal processing circuit.
Claims (1)
出力信号の送出を制御するゲートと、ゲートを介して加
えられるクロックパルスに従って複数ビットのデジタル
信号を取り込む第１のラッチと、第１のラッチと共通の
クロックパルスに従って第１のラッチの出力信号を取り
込む第２のラッチと、これら第１、第２のラッチの出力
信号を照合して信号の変化を検出する信号変化検出回路
と、信号変化検出回路の出力信号、設定切換信号、取り
込み指令信号、取り込み完了信号が加えられ設定状態に
応じた所定の信号をゲート及び信号処理回路に送出して
ゲートの開閉及び信号処理回路の信号取り込みを制御す
る制御回路と、制御回路から加えられる取り込み開始信
号に従って第１のラッチの出力信号を取り込み取り込み
が完了した時点で制御回路に取り込み完了信号を送出す
る信号処理回路とからなるデジタル信号入力装置。a clock pulse generation circuit; a gate that controls the output signal of the clock pulse generation circuit; a first latch that captures a multi-bit digital signal in accordance with the clock pulse applied via the gate; a second latch that captures the output signal of the first latch in accordance with a clock pulse; a signal change detection circuit that detects a change in the signal by comparing the output signals of the first and second latches; A control circuit to which an output signal, a setting switching signal, a capture command signal, and a capture completion signal are added, and which sends a predetermined signal according to the setting state to the gate and the signal processing circuit to control opening/closing of the gate and signal capture by the signal processing circuit. and a signal processing circuit that receives the output signal of the first latch in accordance with a capture start signal applied from the control circuit and sends a capture completion signal to the control circuit when the capture is completed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15620182U JPS5963739U (en) | 1982-10-15 | 1982-10-15 | Digital signal input device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15620182U JPS5963739U (en) | 1982-10-15 | 1982-10-15 | Digital signal input device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5963739U true JPS5963739U (en) | 1984-04-26 |
Family
ID=30344747
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15620182U Pending JPS5963739U (en) | 1982-10-15 | 1982-10-15 | Digital signal input device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5963739U (en) |
-
1982
- 1982-10-15 JP JP15620182U patent/JPS5963739U/en active Pending
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