JPH0485926A - Manufacturing method of semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for manufacturing semiconductor devices, and is particularly suitable for use in manufacturing MO8 integrated circuit devices.・In particular, in the sense that the advantage of low power consumption can be fully utilized, the high degree of integration is unrivaled by other semiconductor devices. One of them is the short-channel effect or bunch-through phenomenon of transistors.The short-channel effect is caused by the miniaturization of the device (L).In particular, as the gate length is reduced, the charge in the channel region under the gate is increased not only by the gate voltage but also by the source and drain regions. The short channel effect is strongly influenced by the depletion layer charge, electric field, and potential distribution, and is a phenomenon that deteriorates the characteristics of the device. The punch-through phenomenon is a phenomenon in which the source-drain diffusion layer distance decreases as the gate length decreases, and the source depletion layer and drain depletion layer connect.＼ The drain current cannot be controlled by the gate voltage.

Therefore, with the current demand for miniaturization of devices, it is desirable to have a method for manufacturing semiconductor devices that prevents the short channel effect and bunch-through phenomenon. Crystalline silicon contacts are no exception (-If undesired impurities or oxides are formed on the surface of polycrystalline silicon during the semiconductor manufacturing process, significant deterioration of contact characteristics is expected as devices become smaller. Therefore, although there is a need for a process that provides stable, reliable and good contact characteristics of gate polycrystalline silicon, an example of a conventional method for manufacturing an NMO8) transistor will be described below. FIG. 4 is a schematic cross-sectional view of the structure of an example of a conventional NMOS transistor.
(IEI about 5 cm-'), then a thin gate oxide film (10 nm to 25 nm) 402 was formed.
Polycrystalline silicon is deposited to a thickness of approximately 300 nm using the cVD method, and then phosphorus is diffused into the polycrystalline silicon by POCps diffusion (approximately IE20cm-" to IE21cm-
'). Gate electrode processing is then performed using photolithography and etching. Next, ion implantation of phosphorus is performed using the gate electrode 403 as a mask (acceleration voltage: 40 KeV, implantation amount: 1 to 3 E l 3 cm-').
, that is, LDD (Lightly Doped
l) forming a rain layer ((a) in the same figure). Next, apply CVD5 i Ox 11 to a thickness of 150 nm to 25 nm on the entire surface of the substrate.
After depositing 0 nm, anisotropic etching is performed, that is, etching the CVD5i02 deposited film thickness only in the vertical direction.
A side wall 405 having a width of 150 nm to 25 Onm is formed on the side surface of the gate electrode 403 . Next, arsenic (80
KeV, 6E15cm-") was implanted to form the source/drain 406 region of NMO3. After that, in order to electrically activate the impurity implanted into the source/drain region, it was heated at a high temperature of about 900°C for about 30 to 40 minutes. Heat treatment is performed (FIG. 2(b)). Next, the phosphor glass film 408 is heated to 70°C.
It is deposited to a thickness of about 0 nm to form an interlayer insulating film. Next, in order to flatten this interlayer insulating film 408, it is heated to about 900°C for about 30°C.
Reflow for about 40 minutes. Then, source/drain electrode windows 409 and gate electrode windows 410 are formed at desired locations by photolithography and etching, and then AL-8i-Cu411 is deposited to a thickness of about 800 nm to form electrodes.

Problems to be Solved by the Invention In the conventional manufacturing method of MOS transistors, the source and drain regions are formed by ion implantation.
The source/drain diffusion layer tends to become deeper due to heat treatment for its electrical activation and subsequent heat treatment during the flow after depositing the phosphor glass film for flattening. The layer is approximately 0.2-0.
If the diffusion layer becomes deeper, the short-channel effect and bunch-through effect of transistors will be promoted, and these effects will become more noticeable as miniaturization and higher integration occur in the future.In order to solve this problem, Therefore, it is possible to form a diffusion layer by reducing the acceleration energy of ion implantation.Both NMO3 and PMO8 diffusion layers require a high dose of about IE15 cm, and it is difficult to realize this with low acceleration energy. Although it is very difficult to do so, it is also possible to reduce the dose and make the diffusion layer shallower (this would increase the layer resistance of the diffusion layer and cause deterioration of device characteristics.

In addition, even though gate polycrystalline silicon electrode windows with highly doped impurities have been miniaturized in response to the demand for finer elements, the polycrystalline silicon surface may become oxidized during the manufacturing process or may not meet the desired requirements. If there is impurity contamination, the impurity concentration on the surface of the gate polycrystalline silicon becomes low, which increases the possibility that the characteristics of the gate electrode contact will deteriorate.

The present invention has been made in view of the above-mentioned problems, and can have the effect of reducing the depth of the diffusion layer in the source/drain region, and also increases the impurity concentration on the gate polycrystalline silicon surface. An object of the present invention is to provide a method for manufacturing a semiconductor device that can stably provide the contact resistance of an electrode window.Means for Solving the ProblemsThe present invention solves the above problems. The method includes a step of forming an impurity layer, a step of forming an amorphous layer in a part of the impurity layer by ion implantation, and a step of applying heat treatment to the semiconductor substrate to concentrate impurities in the amorphous layer. A method of manufacturing a semiconductor device is characterized in that:

Further, the invention is characterized in that the semiconductor substrate is made amorphous by ion-implanting a Group 4 element, fluorine, fluoride, or an inert gas. a step of forming polycrystalline silicon on the gate oxide film, a step of diffusing impurities into the polycrystalline silicon, and a step of forming a gate electrode by patterning the polycrystalline silicon. , forming a source/drain layer by ion implantation using the gate electrode as a mask; forming an amorphous layer by ion implantation into the impurity layer on the semiconductor substrate and a part of the gate electrode; A method for manufacturing a semiconductor device comprising the step of applying heat treatment to an electrode and concentrating impurities in the amorphous layer. Therefore, the depth of the source-drain diffusion layer can be easily reduced, the short channel effect and the bunch-through phenomenon can be suppressed, and the electrode window contact characteristics of the gate polycrystalline silicon can be stably provided. It is possible to obtain a fine semiconductor device with good characteristics and high reliability. NMO3
In Fig. 1(a), an example is shown in which a P-type silicon substrate 1. A P-well layer 101101 (about IEI 5") where NMO3 is formed is provided in the OO. After forming a thin gate oxide film 102 (10 nm to 25 nm), polycrystalline silicon is deposited to a thickness of ~300 nm by CVD method4. Then, POCIs is diffused. Accordingly, polycrystalline silicon is doped with phosphorus to an extent of about IE21 cm-'' to lower the resistance.

Next, the polycrystalline silicon film is processed into a gate electrode by photolithography and etching.

Next, using this gate electrode 103 as a mask, phosphorus is ion-implanted (acceleration voltage: 40 KeV, implantation amount: 1 to 3E13 cm)
1(b), an n- layer 104 is formed so that the l- surface concentration is about IE18 cm-3, and then an insulating film such as a CV layer is formed on the entire surface of the substrate.
The CVDSiO2 film was deposited to a thickness of 150-250nm and was anisotropically etched, that is, the CVDSiO2 film was etched only in the vertical direction.
A side wall 105 having a width of 150 to 25 Onm is formed on the side wall of the gate electrode 103 by etching the deposited film thickness. 4 Next, arsenic (80 KeV, 6E15 cm-") is implanted using the gate electrode with the side wall as a mask. After forming the source/drain 106 region, as shown in FIG. 1(C), this step is one of the features of the present invention. 15cm-
ion implantation in the source-drain layer and gate polycrystalline silicon.
An amorphous layer 107 is formed approximately 50 nm from the gate polycrystalline silicon surface.

Next, heat treatment is applied at 900°C for about 30 minutes. Then, as shown in FIG. 1(d), phosphorus and arsenic will pile up in the amorphous layer 107 in the source/drain layer, and the concentration will become high approximately 50 nm from the surface of the source/drain layer. The reason for this is that the source/drain diffusion layer can be made shallow (because impurities in the semiconductor substrate (in this case, arsenic phosphorus) have gathered).A similar phenomenon also occurs in the gate polycrystalline silicon 103.

For example, even if impurities are formed in the gate polycrystalline silicon or an oxide film is formed on the surface of the polycrystalline silicon before this heat treatment, and the impurity concentration (in this case, the phosphorus concentration) on the surface becomes low (an abnormal increase in contact resistance occurs). expected), by using the present invention approximately 50 nm from the gate polycrystalline silicon surface.
It is possible to increase the impurity concentration (in this case, the phosphorus concentration) at a position of about nm, and it is possible to provide stable and good contact characteristics of the gate polycrystalline silicon electrode. The 4th family of Yuan Qin
Alternatively, a Group 4 fluoride may be used (in addition, it is a substance with a small atomic weight such as fluorine, and its conductivity type does not adversely affect the device, so it can be used as an ion implantation material for amorphous formation. Also, if the conductivity type of the source/drain layer and the gate polycrystalline silicon are the same, the ion species with the same conductivity type can be used. It goes without saying that a fluoride of the same conductivity type may also be used.
In Figure (e), a glass film 108 is deposited to a thickness of about 700 nm to form an interlayer insulating film.Next, in order to flatten this interlayer insulating film, reflowing is performed at about 900°C for about 30 to 40 degrees.Then, photolithography is performed. A source/drain electrode window 109 and a gate electrode window 110 are formed at desired locations using techniques and etching. Then, an AL-8i-Cu film 111 is deposited to a thickness of about 800 nm and processed to form electrodes. Impurities collect in the amorphous layer. I would like to supplement the data on this phenomenon.Here are the results of an experiment in which BF2, a fluoride of the opposite conductivity type, was implanted into phosphorous-diffused gate polycrystalline silicon and heat-treated. Assuming that impurities of the opposite conductivity type (P type) such as B are introduced into the contact area (although an abnormal increase in contact resistance is expected due to B contamination alone), ions, which are a feature of the present invention, are added to the contact resistance. This is equivalent to an experiment to determine what happens to the contact resistance of gate polycrystalline silicon when an amorphous layer is created by implantation and then heat treated.
A sample in which BF2 is not implanted into 300 nm polycrystalline silicon with a high concentration of phosphorus diffused at about E20cm-'', and 40k
A sample injected at eV, 3E15cm-' was prepared, and its equilibrium was heat-treated at 900℃ for 40 minutes in a N2 atmosphere.
Then, interlayer trap contacts and aluminum electrodes were formed.
FIG. 2 shows the contact resistance between a polycrystalline silicon electrode with a diameter of 2.0 μm and an aluminum electrode measured by the Kelvin method for two samples.

The difference in contact resistance between samples in which BF2 was implanted under the conditions of 40 keV and 3E15 cm-'' and samples in which no implantation was made was only about a three-fold increase.When BF2 was implanted under the above conditions, the concentration of B on the polycrystalline silicon surface increased. The concentration of P (phosphorus) is expected to be about 3E20cm-', and an abnormal increase in resistance is expected due to the offsetting effect.However, in reality, the increase is only about three times. BF2 on doped polycrystalline silicon at 40 keV
, P (phosphorus), B, F of the sample injected at 3E15cm-”
The SIMS analysis results are shown. As is clear from the figure, BF
P (phosphorus) on the surface piles up due to the injection of 2.
I know what you're doing. This (approximately 100 nm from the polycrystalline silicon surface became amorphous due to BF implantation, and P (phosphorus) piled up due to subsequent heat treatment). As explained above, the present invention takes advantage of the phenomenon in which impurities gather in the amorphous area due to heat treatment, resulting in stable gate polycrystalline silicon contact characteristics. It also has the effect of making the source/drain layer shallower.
It is possible to provide a stable and good semiconductor device that does not cause punch-through phenomenon or short channel effect, and it is also possible to provide an ideal method for manufacturing a semiconductor device. What is the heat treatment performed?
This is a heat treatment conventionally required to activate the source/drain layer, and in the end, there is only an additional step of ion implantation to form an amorphous layer, and there is no significant difference in throughput.

As described above, conventionally, the source/drain diffusion layer was made deeper by adding heat treatment, but with the present invention, the diffusion layer does not become deeper even if heat treatment is applied, and it is also made amorphous by lion implantation. It is possible to increase the concentration of the impurity layer at a desired location by simply changing the conditions of It is also possible to provide stable and good characteristics.

In this example, NMO3 is used as an example for explanation (P
It goes without saying that it can also be used for the source drain and gate polycrystalline silicon of MOS transistors (this example is a MOS with a well structure). If a P-type substrate is used for NMO3 and an N-type substrate is used for PMO3, a well structure is not particularly necessary.Also, depending on whether or not a well structure is used, the conductivity type of the substrate can be either N or P. In this example, the conductivity type of the source/drain layer and the gate polycrystalline silicon are the same (Ly and L do not matter if they are different). The ion implantation for forming the source/drain layer amorphous layer and the ion implantation for forming the gate polycrystalline amorphous layer are performed separately. The present invention may also be carried out in a CMO3 structure.In that case, the ion implantation material for forming the amorphous layer may be a Group 4 element such as silicon, a fluoride of a Group 4 element, or an inert gas. I,% or cmNMO is desirable.
When making the source drain and N-type gate polycrystalline silicon of No. 3 amorphous, implant N-type ion species or its fluoride. When making the source drain and P-type gate polycrystalline silicon of PMO3 amorphous, use P. In addition, the embodiments of the present invention are applicable to semiconductor devices having an LDD structure, especially DDD (Double Diode).
Semiconductor device with fused drain) structure
It goes without saying that a single drain type semiconductor device may also be used (t'V) Effects of the Invention As is clear from the above explanation, according to the present invention, the depth of the source/drain diffusion layer can be made shallow, resulting in short channel effect and bunch-through effect. In addition, it is possible to obtain highly reliable fine semiconductor devices with stable and good contact characteristics on the gate polycrystalline silicon surface.

[Brief explanation of the drawing]

Fig. 1 is a cross-sectional view of the process flow of an NMO3 transistor in an embodiment of the present invention. Fig. 2 is a contact resistance characteristic diagram measured by the Kelvin method when BF2 is implanted into phosphorus-doped polycrystalline silicon and when BF2 is not implanted. are P (phosphorus') and B when BF2 is implanted into phosphorus-doped polycrystalline silicon.
, F SIMS analysis characteristic doctor Figure 4 is a cross-sectional view of the structure of an NMO3) transistor created using a conventional manufacturing method.
...P well 102,402...Gate oxidation I
L103.403... Boot electrode 104,404.
・・n-seed 105.405・・Side wall (Cv
DSi02 film), 106,406... Source/drain @ 107... Amorphous Ji 108,408...
...phosphorus glass [109,409 source drain electrode λ
110,410...gate electrode window 111,411-
AL-81-CuWL 300... Name of Phosphorus Bail Ass agent Patent attorney Shigetaka Awano and 1 other person 103 Boot electrode 100 type silicon plate diagram roq \ Norst 1. Inden l◆C0NcENT with bow
RATEON (atoms/cc) Figure 15F Doe λN (cm-) Figure

Claims (11)

[Claims] (1) A step of forming an impurity layer on a semiconductor substrate, a step of forming an amorphous layer in a part of the impurity layer by ion implantation, and a step of applying heat treatment to the semiconductor substrate to concentrate the impurity in the amorphous layer. A method for manufacturing a semiconductor device, comprising the step of: 2. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor substrate is made amorphous by ion-implanting a Group 4 element. (3) The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor substrate is made amorphous by ion-implanting fluorine. (4) The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor substrate is made amorphous by ion-implanting fluoride. (5) The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor substrate is made amorphous by ion-implanting an inert gas. (6) Forming a gate oxide film on a silicon substrate, forming polycrystalline silicon on the gate oxide film, diffusing impurities into the polycrystalline silicon, and patterning the polycrystalline silicon. forming a gate electrode by ion implantation using the gate electrode as a mask; forming a source/drain layer by ion implantation using the gate electrode as a mask; and forming an amorphous layer by ion implantation into the impurity layer on the semiconductor substrate and a part of the gate electrode. 1. A method for manufacturing a semiconductor device, comprising the steps of: forming the semiconductor substrate and the gate electrode; and applying heat treatment to the semiconductor substrate and the gate electrode to concentrate impurities in the amorphous layer. (7) The method of manufacturing a semiconductor device according to claim 6, wherein the semiconductor substrate is made amorphous by ion-implanting a Group 4 element. (8) The method for manufacturing a semiconductor device according to claim 6, wherein the semiconductor substrate is made amorphous by ion-implanting fluorine. (9) The method of manufacturing a semiconductor device according to claim 6, wherein the semiconductor substrate is made amorphous by ion-implanting an inert gas. (10) The method for manufacturing a semiconductor device according to claim 6, wherein the source/drain layer and the gate electrode impurity have the same conductivity type, and the ion species used in the ion implantation to form the amorphous layer is the same as the conductivity type. . (11) The source/drain layer and the gate electrode impurity have the same conductivity type, and the ion species for the amorphous layer forming ion implantation is a fluoride having the same conductivity type.
A method of manufacturing the semiconductor device described above.