JPH0485968A - Mos semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent a decrease in gm of a transistor and to improve the operating rapidity of a semiconductor device by providing two gate electrodes at a gap of twice or below as large as the thickness of a sidewall insulating film, and providing a high concentration diffused layer between the two electrodes. CONSTITUTION:Two gate electrodes 4a, 4b are formed in proximity on a p-type silicon substrate l through a gate insulating film 3 to be surrounded by an element isolating region 2. A sidewall insulating film 5 is formed at the sidewalls of the electrodes 4a, 4b, and the sidewall insulating films of the opposed side of the electrodes are removed. A low concentration n-type diffused layer 6 is formed in a self-alignment with the region 2 and the electrodes 4a, 4b, and a high concentration n-type diffused layer 7 is formed in a self-alignment with the region 2, the electrodes 4a, 4b and the film 5. Thus, two transistors can be connected by a low resistance, thereby accelerating its operating speed.

Description

[Detailed Description of the Invention] [Industrial Field of Application] The present invention relates to an MO8 type semiconductor device 1, and in particular, to an L D
A MOS type semiconductor device having a MOS transistor having a D (Lightly Doped Drain) structure and a method for manufacturing the same are described.

[Prior Art] As shown in FIG. 5, a MOS type semiconductor device having an LDD structure has an element isolation region 2 provided on a p-type silicon substrate 1.
, a gate electrode 4 formed through a gate insulating film 3 , a sidewall insulating film 5 provided on the side wall of the gate electrode 4 , and a low voltage layer formed in a self-aligned manner between the gate electrode 4 and the element isolation region 2 . It is composed of a doped n-type diffusion layer 6 and a highly doped n-type doped layer 7 formed in self-alignment with the gate electrode ff14, the sidewall insulating film 5, and the element isolation region 2.

The method for manufacturing the above-mentioned semiconductor device is to form a gate electrode by a known semiconductor device manufacturing method, and then form a low concentration n-type diffusion layer 6 by ion implantation of P (phosphorous) using the gate electrode 4 as a mask. Then, after forming a sidewall insulating film 5 on the sidewalls of the gate electrode 4, a high concentration n-type diffusion layer 7 is formed by ion implantation of As<arsenic) using the gate electrode 4 and the sidewall insulating film 5 as masks. method is commonly used.

[Problem M to be solved by the invention] In the conventional MOS semiconductor device described above, the thickness of the sidewall insulating film depends on the pattern of the gate electrode (width, length,
The thickness was uniform within the chip, regardless of the size of the spacing, etc. Therefore, as miniaturization progresses, in the case of a structure in which the gate electrodes are close together as shown in FIG.
(the sidewall insulating films between the gate electrodes come into contact with each other), and no high concentration diffusion layer is formed between the gate electrodes. Therefore,
Since the transistors are connected only through the low concentration diffusion region, a problem arises in that the diffusion layer wiring between the transistors has a very high resistance.

[Means for Solving the Problems] A MOS type semiconductor device according to the present invention has an insulating film that serves as a mask for ion implantation formed on the side wall of a gate electrode, a low concentration impurity diffusion layer formed in a self-aligned manner with the gate electrode, A high concentration impurity diffusion layer is formed using the insulating film to be spaced apart from the gate electrode, and the distance between two adjacent gate electrodes facing each other is 2 times the thickness of the insulating film.
In the portion where the thickness is less than twice as large, a high concentration impurity diffusion layer is formed in a self-aligned manner with the gate electrode.

[Example] Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view showing one embodiment of the present invention. 1st
As shown in the figure, in the MOS type semiconductor device of this embodiment, a gate insulating film 3 is formed on a p-type silicon substrate l.
Two gate poles 4a and 4b are formed in close proximity to each other and surrounded by the element isolation region 2. Gate T! A sidewall insulating film 5 is formed on the sidewalls of ji 4 a and 4b, but the sidewall insulating film on the side where the gate electrodes face each other is removed. Then, a low concentration n-type diffusion layer (hereinafter referred to as an n-type diffusion layer) 6 is formed in self-alignment with the element isolation region 2 and the gate electrodes 4a and 4b, and the element isolation region 2 and the gate electrodes 4a and 4b are self-aligned. , 4b and the sidewall insulating film 5, a high concentration n-type diffusion layer (hereinafter referred to as an n+ type diffusion layer) 7 is formed.

According to this embodiment, there is a low resistance n between the two gate electrodes.
Since the +-type scattering layer 7 is formed, the two transistors can be connected with low resistance, and the operation speed can be increased.

Next, the manufacturing method of this example will be described with reference to FIGS. 2a to 2e, which are cross-sectional views of the manufacturing process for realizing this example.

First, as shown in FIG. 2(a), an element isolation region 2 is formed on a p-type silicon substrate 1 using a commonly used method.
, and gate electrodes 4a and 4b are formed on the silicon substrate therebetween with a gate insulating film 3 interposed therebetween, with an interval of 400 nm.

Next, using the gate electrodes 4a and 4b and the element isolation region 2 as a mask, P (phosphorus) is ion-implanted at 5X IQ 1.
Implant about 3 am-2 to form an n-type diffusion layer 6 [
Figure 2(b)]. Subsequently, a silicon oxide film 5a is deposited on the entire surface by the CVD method to a thickness of 200 nm [see FIG.
)]. Next, by performing anisotropic processing and quenching, a sidewall insulating film 5 is formed, leaving the silicon oxide film selectively on the sidewalls of the gate electrodes 4a and 4b. At this time, the gate electrodes 4a, 4
Since the distance b is 400 nm, the side wall insulating films between the two electrodes are in contact with each other, and the space between the two electrodes 8ii is filled with an insulating film. Therefore, a photoresist film 8 is formed to expose this portion (FIG. 2(d)), and using this as a mask, the sidewall insulating film 5 between the gate electrodes 4a and 4b is removed, and then the photoresist film 8 is removed. Peel off [Figure 2 (e)
]. Next, As (arsenic) was ion-implanted at 5X
By implanting about 1015 cm@-2 to form an n-type scattering layer 7, the semiconductor device shown in FIG. 1 can be obtained.

FIG. 3 is a sectional view showing another embodiment of the present invention. In the same figure, the same reference numerals are given to the same parts as those in the embodiment shown in FIG. Insulation 1gl5 is left unremoved. However, since the n1 type diffusion layer 7 is formed under this insulating film,
As in the previous embodiment, the two transistors are connected by a low resistance diffusion layer.

Next, the manufacturing method of this example will be explained with reference to FIGS. 4(a) to 4(d). Also in the manufacturing method of this example, the second
Since the steps up to the step shown in FIG. 2(b) are the same as in the previous embodiment, FIG. 2(b) is shown in FIG. 4(a), and the explanation up to that point will be omitted.

After completing the steps up to FIG. 4(a), the gate electrode 4a
, a photoresist film 8 is formed so that the gap between the gate electrodes 4a and 4b is exposed, and using this as a mask, As (arsenic) ions are implanted onto the substrate between the gate electrodes 4a and 4b. A diffused layer 7 is formed [FIG. 4(b)].

After peeling off the photoresist WA8, a silicon oxide film 5 with a thickness of 200 nm is deposited on the entire surface by CVD method [Fig. 4(c)], and sidewall insulation is removed by commonly used anisotropic etch-back. Forming the film 5 [Fig. 4(d)]
], then the element isolation region 2, the gate electrodes 4a, 4b
Then, using the sidewall insulating film 5 as a mask, As is ion-implanted to form an n+ type scattering layer 7, thereby obtaining the semiconductor device shown in FIG. 3.

According to this embodiment, as in the previous embodiment, the gate electrode 4a
Since the sidewall insulating film 5 between the gate electrodes 4a and 4b is not removed, the edge difference between the gate electrodes 4a and 4b is alleviated, and the flatness of the interlayer film formed thereafter is improved.

[Effects of the Invention] As explained above, the present invention provides an advantageous effect when two gate electrodes are spaced apart from each other by less than twice the thickness of the sidewall insulating film in an MO5 type semiconductor device having an LDD structure. ,2
Since a highly concentrated diffusion layer is provided between two gate electrodes, the present invention eliminates the need to insert a high resistance in series with the transistor as in the conventional example even if miniaturization progresses. It is possible to prevent a decrease in performance and improve the operating speed of the semiconductor device.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing one embodiment of the present invention, and FIG.
) to (e) are process cross-sectional views for explaining the manufacturing method, FIG. 3 is a cross-sectional view showing another embodiment of the present invention, and FIG.
Figures (a) to (d) are process cross-sectional views for explaining the manufacturing method, Figure 5 is a cross-sectional view of the conventional example, and Figure 6 is a cross-sectional view for explaining the problems of the conventional example. be. 1...p-type silicon substrate, 2...element isolation region,
3... Gate oxide film, 4.4a, 4b... Gate electrode, 5... Sidewall insulating film, 5a...
Silicon oxide film, 6...Low concentration n-type diffusion layer (n
type diffusion layer), 7...high concentration n-type diffusion layer (n +
type diffusion layer), 8... photoresist film.

Claims (3)

[Claims] (1) In a MOS semiconductor device having two insulated gate field effect transistors provided close to each other, surfaces of the semiconductor substrate on sides of gate electrodes of the two insulated gate field effect transistors facing each other. A high concentration impurity diffusion layer is provided in the region and is formed in a self-aligned manner with the gate electrode, and a high concentration impurity diffusion layer is formed in a surface region of the semiconductor substrate on the other side of the gate electrode in a self-aligned manner with the gate electrode. 1. A MOS semiconductor device comprising: a low concentration impurity diffusion layer; and a high concentration impurity diffusion layer formed in self-alignment with a sidewall insulating film provided on a sidewall of the gate electrode. (2) forming a plurality of gate electrodes including two gate electrodes close to each other with a gate insulating film interposed therebetween on a semiconductor substrate of a first conductivity type; and using the plurality of gate electrodes as a mask, the surface of the semiconductor substrate a step of introducing an impurity of a second conductivity type at a low concentration into the gate electrode; a step of depositing an insulating film and subjecting it to anisotropic etch-back to form a sidewall insulating film on the side wall of the gate electrode; a step of etching away a sidewall insulating film buried between two gate electrodes; and a step of introducing a second conductivity type impurity into the surface of the semiconductor substrate at a high concentration using the gate electrode and the sidewall insulating film as a mask. A method for manufacturing a MOS type semiconductor device. (3) Forming a plurality of gate electrodes on a semiconductor substrate of a first conductivity type via a gate insulating film, and using the plurality of gate electrodes as a mask, impurities of a second conductivity type are reduced to the surface of the semiconductor substrate. and a step of forming a mask that exposes the surface of the semiconductor substrate between two gate electrodes formed at a distance of less than twice the thickness of a sidewall insulating film to be formed later. a step of introducing a second conductivity type impurity into the exposed portion of the semiconductor substrate at a high concentration; and depositing an insulating film and subjecting it to anisotropic etchback to form a sidewall insulating film on the sidewall of the gate electrode. A method for manufacturing a MOS type semiconductor device, comprising: forming a second conductivity type impurity into the surface of the semiconductor substrate at a high concentration using the gate electrode and the sidewall insulating film as a mask.