JPH048661Y2 - - Google Patents

Description

[Detailed explanation of the invention] This invention is a field effect transistor (hereinafter referred to as FET).
This relates to a bias circuit using

Today, digital circuits such as analog-to-digital converters and digital-to-analog converters,
Integrated circuit devices that perform digital data processing using analog circuits are well known, but in such integrated circuit devices, the threshold voltage V _T of the FET that makes up the circuit usually varies due to manufacturing variations. There is a variation of ±20% to ±30%. In a digital circuit made up of an integrated circuit, only the presence or absence of a signal is important, so the above-mentioned variation in threshold voltage is within a permissible range. However, in conventional analog circuits, especially bias circuits, it is not possible to obtain fully satisfactory input/output characteristics due to variations in threshold voltage, resulting in deterioration of characteristics or a decrease in the yield of non-defective products, increasing the cost of integrated circuit devices. Ta. 1 and 3 show examples of bias circuits using n-channel enhancement type FETs that have been commonly used in the past. First, in the circuit configuration in Fig. 1, the drain of FETM ₁ is connected to the first power supply terminal 3 (+
V _DD ), its gate is connected to input terminal 1, its lease is connected to output terminal 2 and one end of constant current source 5, and the other end of constant current source 5 is connected to second power supply terminal 4 (-V _SS )It is connected to the. Input terminal 1 has
A constant input voltage V _IN is input, and the constant current source 5 causes a constant current I ₁ to flow from the lease of the FETM ₁ to the second power supply terminal 4 . At this time, output terminal 2 has an output voltage of
Output V _OUT . Now, in the circuit configuration shown in FIG. 1, the drain current of FETM ₁ is equal to the constant current I ₁ of the constant current source 5, and the gate-source voltage V _GS ¹ is
This is the difference between the input voltage and output voltage (V _IN − V _OUT ).
Since the drain current of FETM ₁ is always constant,
Fluctuations in the threshold voltage V _T appear as fluctuations in V _OUT , and as shown in FIG. 2, the bias circuit has a disadvantage in that the output voltage increases or decreases due to variations in V _T . Next, the circuit configuration of FIG. 3 uses an n-channel with the drain gate shorted instead of the constant current source 5 of the circuit configuration of FIG. 1.
FETM ₂ is connected. In this circuit configuration, the drain currents of FETM ₁ and M ₂ are equal, and the gate-source voltage V _GS of FETM ₂ becomes V _OUT . Now, if the effective width-to-length ratios of the channels of FETM ₁ and M ₂ are (Z/L) ₁ and (Z/L) ₂ , then the output voltage for the variation in V _T in this circuit configuration is
The fluctuation of V _OUT becomes constant as shown in FIG. 4 when (Z/L) ₁ = (Z/L) _{2 and} the output voltage V _OUT becomes 1/2 V _IN . However, in this circuit configuration, the threshold voltage V _T of FETM ₁ and M ₂ becomes large, and when it becomes V _IN 2Vr and V _GS V _T , the drain current I _D of FETM ₁ and M ₂ becomes 0,
There is a drawback as a bias circuit that the output impedance of the output terminal 2 becomes very high. or,
As mentioned above, the output voltage V _OUT which is not affected by the variation in V _T is only when 1/2 V _IN , which is subject to circuit design constraints. As mentioned above, conventional
Bias circuits using FETs have disadvantages in that the output voltage increases or decreases due to manufacturing variations in V _T , or the output impedance becomes extremely high.This disadvantage deteriorates the characteristics of integrated circuit devices. This was one of the contributing factors.

An object of the present invention is to provide a bias circuit that can be integrated with a small number of elements and solves the above-mentioned problems.

According to the present invention, the input section includes an input terminal, a first field effect transistor having a gate electrode connected to the input terminal and a source electrode and a drain electrode, and a source electrode of the first field effect transistor. a main constant current source with one end connected to;
An auxiliary current source consisting of a second field effect transistor whose drain electrode and gate electrode are connected to the source electrode of the first field effect transistor and whose source is held at a constant potential; A bias circuit is obtained including a connected output terminal.

The present invention will be described in detail below with reference to the drawings.

FIG. 5 shows an embodiment of a bias circuit using the present invention. FETM ₁ and M ₂ in FIG. 5 are n-channel enhancement type FETs. FETM ₁ constitutes an input section, with its gate connected to input terminal 1, its drain connected to first power supply terminal 3 (V _DD ), and its source connected to output terminal 2. FETM ₂ constitutes an auxiliary current source, with gate and The drain is short-connected to the output terminal input,
Further, the source is connected to the second power supply terminal 4, (-V _SS ). Further, a constant current source 5, which is a main constant current source, is connected between the output terminal input and the source of the FETM ₂ . Input terminal 1 has a constant input voltage V _IN
is input, the constant current I ₁ of the constant current source 5 is set, and the output voltage V _OUT is outputted to the output terminal 2. In this circuit configuration, the drain current of FETM ₁ is
Drain current of FETM ₂ and constant current of constant current source 5
It becomes the sum with I ₁ . Now, since the relationship between the FETM ₁ and the constant current source 5 is the same as the configuration shown in FIG. 1, as shown by the broken line 1 in FIG. 6, V _OUT increases as V _T decreases. At this time, the V _T of FETM ₂ also decreases along with FETM ₁ , so the drain current of FETM ₂ increases,
Increase the drain current of FETM ₁ . Accordingly
An increase in the drain current of FETM ₁ results in an increase in the gate-source voltage (V _IN - V _OUT ) of M ₁ . Since V _IN is now constant, V _OUT will decrease. Therefore, the variation in the output voltage V _OUT due to the variation in V _T in this circuit configuration is as shown by the solid line 2 in Figure 3b.
It is clamped from the point where the drain current of FETM ₂ starts to increase. Furthermore, by constantly passing a constant current I ₁ through the FETM ₁ , an increase in output impedance can be prevented. Therefore, the bias circuit of FIG. 5 can control V _T by appropriately selecting the effective width-to-length ratio (Z/L) of the channels of FETM ₁ and M ₂ and the constant current value of the constant current source. It is possible to suppress fluctuations in V _OUT due to manufacturing variations and prevent an increase in output impedance. FIG. 7 shows another embodiment of the bias circuit according to the present invention. The circuit configuration of FIG. ₇ is the same as the circuit configuration _{of FIG} .
Connect the gate of FETM ₃ to input terminal 1,
The back gates of FETM ₁ and M ₃ are connected to output terminal 2. This circuit configuration has a gate grounded between the first power supply terminal 3 (+V _DD ) and FETM ₁ .
By connecting FETM ₃ , the first power supply terminal 3
For variations in the power supply connected to the output voltage
This makes it possible to prevent fluctuations in V _OUT .

Although the bias circuit of the present invention described above is an embodiment using an n-channel FET, it is not limited to this, and it is of course possible to implement it using a p-channel FET.

As described above, the bias circuit provided by the present invention is characterized by being able to suppress fluctuations in output voltage due to manufacturing variations in threshold voltage and prevent increases in output impedance, and has a wide range of applications in this technical field. It is a wide bias circuit.

[Brief explanation of the drawing]

Figure 1 shows a conventional bias circuit, Figure 2 shows the characteristics of the circuit in Figure 1, Figure 3 shows another conventional bias circuit, and Figure 4 shows the characteristics of the circuit in Figure 3. 5 is a diagram showing a bias circuit according to one embodiment of the present invention, FIG. 6 is a diagram showing characteristics of the circuit of FIG. 5, and FIG. 7 is a diagram showing another embodiment of the present invention. . _M1 to _M2 ...Transistor, _I1 ...Current source.

Claims (1)

[Scope of utility model registration request] a first electrode having an input terminal, a gate electrode connected to the input terminal, and a source electrode and a drain electrode;
an input section including a field effect transistor; a main constant current source having one end connected to the source electrode of the first field effect transistor; a drain connected to the source electrode of the first field effect transistor; A bias circuit comprising: an auxiliary current source including a second field effect transistor whose electrode and gate electrode are connected and whose source electrode is kept at a constant potential.