JPH0486694A - Color signal generator for crt - Google Patents

Abstract

PURPOSE:To facilitate the use of a memory having the access time larger by N times than the access time of the conventional device by connecting a table which emits the data for N picture element components in parallel to the rear of a memory section. CONSTITUTION:The memory section 2 stores the color numbers of a CRT 6 and outputs the color numbers in parallel. A color look-up table 3 is inputted as an address with the output of the memory section 2 and outputs the data corresponding to the color numbers in parallel. A parallel/series conversion section 4 is inputted in parallel with the parallel output of the table 3 and outputs the data in series by one picture element component each. D/A converters 5A to 5C subject the output of the converting section 4 to D/A conversion and add the converted outputs to the CRT 6. For example, the color numbers for the N picture element components are read out in parallel from the memory section 2 and the color data for the N picture element components are received by the table 3 constituted of N-pieces of memories. The table 3 is constituted of the memories of the access time larger by N times than the access time of the conventional device in this way.

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention relates to a color signal generation at for CRT that divides the screen of the CRT into a plurality of pixels and controls the color displayed for each pixel. be.

[Conventional technology] Next, the configuration of the conventional device will be explained with reference to FIG.

In Figure 3, 1 is the CPU, 2 is the memory section, and 5A to 5C are the D/
A converter, 6 is CRT, 7 is parallel/serial converter (hereinafter referred to as
It is called the PS converter. ), 8 is a color lookup table (hereinafter simply referred to as a table), 21 and 22 are memories, and 71 and 72 are shift registers (hereinafter referred to as SR).

), and the CRT8 is for color.

The memory section 2 is composed of a memory 21 and a memory 22.

The color numbers of the pixels of the CRT 6 for one screen are written into the memories 21 and 22 by the CPU 1.

Then, the memories 21 and 22 output N-pixel bone color numbers in parallel on the screen in the scanning line direction.

In FIG. 3, the memory section 2 outputs N=4 pixel color numbers in parallel, and the memories 21 and 22 each have a 4-bit parallel output.

The color number is used to specify the color to be displayed on the pixels of the CRT 8, and serves as an address input for a table 8, which will be described later.

In FIG. 3, the color number is a two-digit binary number, and as will be explained in Table 8, there are four types of colors that can be simultaneously displayed on the screen of the CRT 8.

The first digit of the color number is stored in the memory 21, and the second digit of the color number is stored in the memory 22.

The ps conversion section 7 is composed of four stages of SRs 71 and 72, and receives color numbers for four pixels from the memory section 2 in parallel.
Output color numbers serially, one pixel at a time.

SR71 receives the 4-bit parallel output of memory 21 in parallel and converts it into serial data.

5R72 converts the 4-bit parallel output of memory 22 into serial data in the same way as SR71.

In other words, the 5R71 serially outputs the first digit data of the color number for four pixels one pixel at a time. Also, 5R72 is 4
The second digit data of the color number for each pixel is output in series for each pixel.

The table 8 is composed of a memory having a 2-bit address input, and stores data corresponding to the color of the screen surface of the CRT 8.

The data in Table 8 is for controlling the brightness of the three primary colors of the CRT 6, and the CRT 6 displays colors corresponding to the brightness of the three primary colors.

The data in table 8 is composed of data 11 to 13.

Data 11 controls the brightness of red color, and data 12 controls the brightness of green color. The data 13 controls the brightness of blue color.

The table 8 uses the output of the PS converter 7, that is, the color number for the first pixel, as an address input, and sends out data corresponding to the color number of that pixel in parallel.

Note that FIG. 3 shows a case where data 11 to 13 are each composed of 2 bits.

In FIG. 3, since the color number is two binary digits, the table 8 stores data at addresses "0" to "3". That is,
If the color number is a two-digit binary number, four types of data can be obtained from the table 8, so four types of colors can be displayed on the screen of the CRT 6 at one time.

Note that in FIG. 3, illustration of means for writing data from the CPUI to the table 8 is omitted.

The D/A converters 5A to 5C are 2-bit D/A converters, and the D/A converter 5A converts the data 11 into a D/A converter.
Drives the R terminal of RT8.

The D/A converter 5B performs D/A conversion on the data 12, and drives the G terminal of the CRT 8 with the converted output.

The D/A converter 5C converts the data 13 from D/A to CRT.
Drives the B terminal of 8.

For example, if you add "11" to D/A converter 5A and "00" to D/A converters 5B and 5C, the CRT
8 displays red.

Next, a storage state diagram of table 8 is shown in FIG.
A display example of 8 is shown in FIG.

FIG. 4 shows a case where four colors, red, green, blue, and white, are displayed on one screen.

In table 8, data for displaying red color is stored at address rOJ, and data for displaying green color is stored at address "1". Further, in the table 8, data for displaying blue color is stored at address "2", and data for displaying white color is stored at address "3".

For example, the color number "01" is stored in the table 8 from the PS converter 7.
is added, table 8 outputs data for displaying the green color of address "1". In this case, data 12 is "11", and data 11 and data 13 are "OO".

FIG. 5 shows a case where there are pixels 61 to 68 for one transmission line of the CRT 6. In FIG.

The actual number of pixels for one scanning line is 400 to 2000.
That's about it.

Pixels 61 and 65 in FIG. 5 have a color number of "00" and display red, and pixels 62 and 68 have a color number of "01" and display green.

Furthermore, pixels 63 and 67 have a color number of "10" and display blue, and pixels 64 and 68 have a color number of "11" and display white.

Next, the time chart of FIG. 3 will be explained with reference to FIG. 6.

FIG. 6 shows the case where N=4, and time T is the horizontal scanning time.

FIG. 6A is a diagram showing the operation cycle of the memory section 2. In FIG. 6th
Time S in Figure A is the starting point of horizontal scanning, and time U is the time T/2 from the starting point.

The memory unit 2 outputs color numbers for four pixels in parallel at time S and time U.

At time S in FIG. 6A, the memory unit 2 stores pixels 61 to 61 in FIG.
64 color numbers are output in parallel, and at time U, color numbers for pixels 65 to 68 are output in parallel.

The PS converter 7 converts the color numbers of the pixels 81 to 68 into serial outputs and adds them to the table 8.

FIG. 6A is an output waveform diagram of table 8, and pixel 61
Data corresponding to color numbers .about.68 are sequentially taken out from table 8 in synchronization with horizontal scanning.

That is, in FIG. 3, if the horizontal scanning time is T, the operation cycle of the table 8 is T/8.

[Problems to be Solved by the Invention] In the conventional device as shown in FIG. 3, since the table 8 is located after the PS converter 7, the following problem occurs when the CRT 6 has a high resolution.

For example, on a high-resolution CRT, one screen is vertical x horizontal = 8
It is composed of 00x1024 pixels.

To prevent eye flickering, it is standard to scan the raster at a speed of 60 screens/a strange rate. In this case, the horizontal scanning time T is approximately 20.8μs=1/(80X800), and the operation time per pixel in Table 8 is 20.8n.
s=8μs/102.

The memory that can be used for table 8 has an access time of 20.3 ns or less, and an ECL element is used.

Since the ECL element has a different power supply voltage from ordinary CMO8, TTL, etc. elements, a power supply exclusively for the ECL element must be prepared.

Furthermore, ECL elements consume a lot of power (and generate high heat, so heat dissipation measures are required.

In this invention, by connecting a table that outputs data for Nll1 elements in parallel after the memory section 2 in FIG. 3, it is possible to use memory for the table, which has an access time N times longer than that of the conventional device. The purpose of the present invention is to provide a color signal generator for CRT.

[Means for Solving the Problems] In order to achieve this object, the present invention includes a memory unit that stores color numbers of each pixel of a CRT and outputs the color numbers in parallel, and an output of the memory unit. a color lookup table which takes address input as an address and outputs data corresponding to the color number in parallel; and a parallel/parallel/color lookup table that takes the parallel outputs of the color lookup table as parallel input and outputs the data for each pixel in series. The outputs of the serial converter and the parallel/serial converter are converted to /A, and the converted output is sent to the CRT.
and a plurality of D/A converters.

[Operation] Next, a configuration diagram of an embodiment according to the present invention will be explained with reference to FIG.

3 in Figure 1 is a table, 31 to 34 are memories, and 4 is a PS.
The conversion units 41 to 46 are SRs, and the others are the same as in FIG. 3.

In other words, in FIG. 1, the PS converter 4 and table 3 are used instead of the PS converter 7 and table 8 in FIG.

The table 3 is connected to the output terminal of the memory section 2, and the PS conversion section 4 is connected to the output terminal of the table 3.

Table 3 is composed of memories 31-34.

Memories 31-34 are the same, have a 2-bit address input, and store the same contents as the memory of table 8 in FIG. That is, table 3 is composed of four tables 8.

The color numbers for four pixels output in parallel from the memory section 2 serve as address inputs to the memories 31 to 34, respectively.

In the configuration of FIG. 1, the memory 31 is connected to the pixels 61 and 6 of FIG.
The memory 32 outputs data corresponding to the color number 5, and the memory 32 outputs data corresponding to the color numbers of pixels 62 and 66.

Further, the memory 33 outputs data corresponding to the color numbers of pixels 63 and 67, and the memory 34 outputs data corresponding to the color numbers of pixels 6-4 and 68.

That is, from table 3, data for every four pixels is taken out as parallel output.

Note that the timing for extracting data from table 3 will be explained in FIG. 2, which will be described later.

The PS converter 4 is composed of four stages of SRs 41 to 46.

SRs 41 to 46 receive data for four pixels from the memories 31 to 34 in parallel and convert it into serial data.

5R41 and 42 receive data 11 for 4 pixels in parallel, convert it to serial data, add it to the D/A converter 5A, and
3.44 receives data 12 for four pixels in parallel, converts it into serial data, and applies it to the D/A converter 5B. And 5
R45 fist 46 converts data 13 for four pixels into serial data in the same way as 5R41-44, and applies it to D/A converter 5C.

Next, the time chart of FIG. 1 will be explained with reference to FIG. 2.

Figure 2 A is the same as Figure 6 A, and Figure 2 B is the same as Figure 6 A.
This is the output waveform of the memory 31.

As shown in Figure 2A, at time S in Figure 2A, the memory 31
outputs data corresponding to the color number of pixel 61, and outputs data corresponding to the color number of pixel 65 at time U.

FIG. 2 is a diagram of the output waveform of the memory 32.

The memory 32 outputs data corresponding to the color number of pixel 62 at time S, and outputs data corresponding to the color number of pixel 66 at time U.

The second figure is an output waveform diagram of the memory 33.

The memory 33 sends out data corresponding to the color number of pixel 63 at time S, and sends out data corresponding to the color number of pixel 67 at time U.

FIG. 2 is an output waveform diagram of the memory 34.

The memory 34 outputs data corresponding to the color number of pixel 64 at time S, and outputs data corresponding to the color number of pixel 68 at time U.

The second graphical power is the output waveform of the PS converter 4, which sequentially sends out data from pixel 61 to pixel 68 in synchronization with horizontal scanning.

As mentioned above, the operation cycle of Table 3 in Fig. 1 is T/2.
It is four times longer than Table 8 in FIG. Therefore, the access time of memories 31-34 may be four times slower than the memory of Table 8 in FIG.

FIG. 1 shows the case where N=4 in the memory section 2, but when N=8, the table 3 is composed of eight memories, and the PS conversion section 4 is composed of eight stages of SRs. In this case, conventionally all
Table 3 with memory that has an access time 8 times greater than
can be configured.

Note that although Fig. 1 shows the case where there are three D/A converters, there are two D/A converters.
The technical scope of this invention also includes the case of .

[Effects of the Invention] According to the present invention, for example, the color numbers for 8 pixels are read out in parallel from the memory section 2, and the color data for the 8 pixels are received in a table made up of 8 memories. Since the table can be constructed using a memory whose access time is 8 times longer than that of the conventional device, the following effects can be obtained.

In other words, even when displaying colors on a high-resolution CRT,
Since the device can be configured with CMO87 or TTL without using an ECL element, power supplies can be unified and power consumption can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of an embodiment according to the present invention, and FIG.
3 is a configuration diagram of the prior art, FIG. 4 is a storage state diagram of table 8, and FIG. 5 is a CRT.
FIG. 6 is a diagram showing the time chart of FIG. 3. 1...CPU12...Memory section, 3.
...Color lookup table (table),
4...Parallel/serial converter (PS converter), 5A
~5C...D/A converter, 6...CR
T17...Parallel/serial conversion section (PS conversion section),
8...Table, 21, 22...Memory, 31-34...Memory, 41-46...
...Shift register (SR), 71, 72...
- Shift register (SR). Agent Patent Attorney Kin Tsukasa Komata Figure Figure Figure Figure Figure Figure T/'8

Claims (1)

[Scope of Claims] 1. A memory unit that stores color numbers of each pixel of a CRT and outputs the color numbers in parallel; and an output of the memory unit is used as an address input, and data corresponding to the color numbers are output in parallel. a color lookup table as an output; a parallel/serial converter that takes the parallel outputs of the color lookup table as parallel inputs and outputs the data for each pixel in series; and an output of the parallel/serial converter. A color signal generating device for a CRT, comprising a plurality of D/A converters that perform D/A conversion and apply the converted output to the CRT.