JPH0486937U - - Google Patents
Info
- Publication number
- JPH0486937U JPH0486937U JP13005190U JP13005190U JPH0486937U JP H0486937 U JPH0486937 U JP H0486937U JP 13005190 U JP13005190 U JP 13005190U JP 13005190 U JP13005190 U JP 13005190U JP H0486937 U JPH0486937 U JP H0486937U
- Authority
- JP
- Japan
- Prior art keywords
- conversion
- bus
- completed
- asynchronous
- asynchronous bus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Information Transfer Systems (AREA)
Description
第１図は、本考案のＡ／ＤＣの制御回路を示す
ブロツク図である。
１……サンプル＆ホールド回路、２……Ａ／Ｄ
変換器、３……３ステート・バツフアー、４……
Ｄタイプフリツプフロツプ、５……タイミング発
生同期式ＰＡＬ。
FIG. 1 is a block diagram showing the control circuit of the A/DC of the present invention. 1...Sample & hold circuit, 2...A/D
Converter, 3... 3-state buffer, 4...
D type flip-flop, 5...timing generation synchronous type PAL.
Claims (1)
変換結果を読み出す命令を発生させるだけで、自
動的にＡ／Ｄ変換開始信号を発生し、これに同期
してタイミング発生回路が動作し、Ａ／Ｄ変換が
終了するまで、非同期バスのバス・マスタを持た
せ、Ａ／Ｄ変換終了と同時に、変換結果を非同期
バスに出力する機能を有することを特徴とするＡ
／ＤＣ制御回路。 In an asynchronous bus such as the VME bus, A/D
Simply by generating a command to read the conversion result, an A/D conversion start signal is automatically generated, the timing generation circuit operates in synchronization with this, and the asynchronous bus bus/digital signal is activated until the A/D conversion is completed. A characterized in that it has a master and has a function of outputting the conversion result to the asynchronous bus at the same time as the A/D conversion is completed.
/DC control circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13005190U JPH0486937U (en) | 1990-11-30 | 1990-11-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13005190U JPH0486937U (en) | 1990-11-30 | 1990-11-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0486937U true JPH0486937U (en) | 1992-07-28 |
Family
ID=31877421
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13005190U Pending JPH0486937U (en) | 1990-11-30 | 1990-11-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0486937U (en) |
-
1990
- 1990-11-30 JP JP13005190U patent/JPH0486937U/ja active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH0486937U (en) | ||
| JPS583780U (en) | Synchronous pulse signal generation circuit | |
| JPS62177122U (en) | ||
| JPS6356826U (en) | ||
| JPH03117947U (en) | ||
| JPS6289880U (en) | ||
| JPH0193829U (en) | ||
| JPS62196430U (en) | ||
| JPH01146640U (en) | ||
| JPS62133473U (en) | ||
| JPS5866891U (en) | Phasing device for run-up inverter | |
| JPS59119668U (en) | Frame pulse generation circuit | |
| JPS62164422U (en) | ||
| JPH01110569U (en) | ||
| JPS63122805U (en) | ||
| JPS639644U (en) | ||
| JPS647474U (en) | ||
| JPS6370758U (en) | ||
| JPH0369970U (en) | ||
| JPH03105084U (en) | ||
| JPH01155546U (en) | ||
| JPS6413331U (en) | ||
| JPS649497U (en) | ||
| JPS63173972U (en) | ||
| JPH01149134U (en) |