JPS62133473U

JPS62133473U -

Info

Publication number: JPS62133473U
Application number: JP2111386U
Authority: JP
Priority date: 1986-02-17
Filing date: 1986-02-17
Publication date: 1987-08-22

Description

[Brief explanation of the drawing]

第１図は本考案の一実施例によるフレームシン
クロナイザのブロツク図を示し、第２図は従来の
フレームシンクロナイザのブロツク図を示す。ま
た、第３図はデイスプレイにおけるアドレス状態
図を、第４図はアドレスパルス生成状態図を、第
５図はアドレス発生回路のブロツク図を示す。１……Ａ／Ｄ変換器、３……フレームメモリ、
４……Ｄ／Ａ変換器、５，６……クロツク発生器
、１１，１２……ラインメモリ。 FIG. 1 shows a block diagram of a frame synchronizer according to an embodiment of the present invention, and FIG. 2 shows a block diagram of a conventional frame synchronizer. Further, FIG. 3 shows an address state diagram in the display, FIG. 4 shows an address pulse generation state diagram, and FIG. 5 shows a block diagram of the address generation circuit. 1...A/D converter, 3...frame memory,
4...D/A converter, 5, 6...Clock generator, 11, 12...Line memory.

Claims

[Scope of utility model registration request]

The first video signal is synchronized with the second video signal with a different synchronization signal.
The frame synchronizer converts the first video signal into a digital video signal using a first clock generating means synchronized with a synchronization signal of the first video signal, and a clock of the first clock generating means. A/D conversion means for converting the digital signal into a signal; two-column line memory for writing the digital signal line by line; a second clock generation means synchronized with a synchronization signal of the second video signal; means for reading each line from the line memory in the two columns by the clock of the clock generating means and writing it into the subsequent frame memory; means for reading from the frame memory; and means for reading from the frame memory read by the reading means. A frame synchronizer comprising: D/A conversion means for converting a digital signal into an analog signal.