JPH0486945U

JPH0486945U -

Info

Publication number: JPH0486945U
Application number: JP1990128109U
Authority: JP
Priority date: 1990-11-30
Filing date: 1990-11-30
Publication date: 1992-07-28

Description

[Brief explanation of the drawing]

第１図は本考案の一実施例のブロツク図である
。１……ＣＰＵ、２……メモリ、３……ユーザ・
モード判別回路、４……アドレス範囲指定レジス
タ、５……アドレス比較回路、６……バス・エラ
ー発生回路、７……１ビツトフラグレジスタ、８
……レジスタアドレス・デコード回路、９……メ
モリアドレス・デコード回路、１０……アンド回
路、Ｒ／……リードライト信号、ＶＩＯ……違
反信号、ＢＥＲＲ……バスエラー信号、……
ライトパルス、ＣＳ……チツプセレクト信号、
……アウトプツトイネーブル信号。 FIG. 1 is a block diagram of one embodiment of the present invention. 1...CPU, 2...Memory, 3...User
Mode discrimination circuit, 4... Address range specification register, 5... Address comparison circuit, 6... Bus error generation circuit, 7... 1-bit flag register, 8
...Register address/decode circuit, 9...Memory address/decode circuit, 10...AND circuit, R/...read/write signal, VIO...violation signal, BERR...bus error signal,...
Light pulse, CS...chip select signal,
...Output enable signal.

Claims

[Claims for Utility Model Registration] An address range designation register 4 into which data designating a write-prohibited range on the memory 2 is written; and an address range designation register 4 in which an address input from the CPU 1 for writing is written. An address comparison circuit 5 outputs a violation signal VIO when the specified data is in the write-prohibited range, and outputs an enable signal E when a function code FC specifying a user mode from the CPU 1 is input. User mode discrimination circuit 3
and a write signal from the CPU 1 and an enable signal E from the user mode discrimination circuit 3.
and the violation signal VIO from the address comparison circuit 5.
is input, a bus error signal B is sent to the CPU 1.
a bus error generation circuit 6 which outputs an ERR to notify write prohibition and also outputs a write inhibit signal; A register address decoder circuit 8 having a function of causing the address range specifying register 4 to write in a write-prohibited address range, and reading the data written in the address range specifying register 4 by inputting the address and read signal R and checking its contents. and an AND circuit 10 that inhibits write addresses to the memory 2 when a write inhibit signal from the bus error generation circuit 6 is input.