JPH048705Y2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Field of Industrial Application The present invention relates to a field discrimination circuit used in television receivers and the like.

(b) Conventional technology For example, in a television receiver, when extracting a VIR signal inserted only in an odd field, or when switching deflection operation between an odd field and an even field, it is necessary to check the current reception of the television signal. It is necessary to determine the field inside,
A field discrimination circuit used in such a case is described in, for example, Japanese Patent Publication No. 54-29224. That is, in this conventional circuit, a logic circuit accurately detects a vertical synchronizing pulse and determines whether a horizontal synchronizing signal exists within 1H (one horizontal scanning period) from the last pulse of the equivalent pulse after this vertical synchronizing pulse. However, the configuration is complicated and the cost is high.

(c) Problems to be solved by the invention The present invention takes the above-mentioned points into consideration and attempts to provide a field discriminating circuit that has a simple circuit configuration and can be realized at low cost.

(d) Means for solving the problem In the present invention, charging of the charging capacitor is started at a timing within the period of the first vertical synchronizing pulse in the composite synchronizing signal, and the first input signal is The present invention includes a first circuit that stops charging the capacitor at the timing of a horizontal drive pulse, and a second circuit that compares and detects the voltage appearing on the capacitor with a constant voltage to obtain a field discrimination output.

(E) Effect Since the first circuit controls the charging/discharging capacitor as described above, the voltage appearing on this capacitor has different magnitudes in the odd field and the even field. Each of the above fields is determined by comparing and detecting a constant voltage with a circuit.

(f) Embodiment FIG. 1 shows a schematic configuration of the main parts of an embodiment of the present invention, in which 1 is a first terminal into which a composite synchronous signal from a synchronous separation circuit (not shown) is introduced, and 2 is a horizontal output. The second terminal to which the horizontal drive pulse from the circuit (not shown) is introduced, 3 is an IC made by Mitsubishi Electric Corporation that has two built-in DFFs (D flip-flops) with set/reset functions. :M74LS74AP.
4 is the first transistor Tr ₁ at the timing described later.
This circuit controls charging and discharging of the capacitor _C3 by the pulse obtained at the collector of the IC3 and the output pulse of the pin of the IC3, and the second to fourth transistors
It consists of Tr ₂ , Tr _3, etc. A comparison detection circuit 5 compares the voltage generated in the capacitor _C3 with a constant voltage, and is composed of fifth to seventh transistors _Tr5 to _Tr7 and the like. Further, numeral 6 denotes a pulse width conversion circuit which receives the collector output pulse of the first transistor Tr ₁ and is composed of eighth and ninth transistors Tr ₈ and Tr ₉ and a differentiating circuit provided between them. Then, by obtaining the output pulse of this pulse width conversion circuit and the output pulse of the detection circuit 5, the IC 3 outputs a field discrimination pulse.

Note that the reset R, data D, trigger T, set S, and output Q terminals of the first D/FF of the IC3 are connected to the ~ pin, and the first
Similar terminals of the 2D/FF are connected to the ~ pin, and the pins serve as a common ground terminal and power supply (+Vcc ₁ ) terminal, respectively.

One embodiment of the present invention is generally constructed as described above, and its operation will be described below with reference to the waveform diagrams of FIGS. 2 to 4.

Now, considering the point in time when the vertical synchronizing pulse portion of the composite synchronizing signal a of the odd field shown in FIG. 2 or the even field shown in FIG. 3 is input to the first terminal 1, the vertical synchronizing pulse portion is At this time, by appropriately selecting the time constant of the integrating circuit 7, _{the first transistor Tr 1 receives} the vertical synchronizing pulse. It is turned on during the first pulse of the second pulse. Then, the second and fourth transistors Tr ₂ and Tr ₄ are turned on one after another, and the capacitor
Charging of C ₃ is started via the fourth transistor Tr ₄ and variable resistor VR ₁ , and the potential at point P gradually rises.

On the other hand, the positive pulse C obtained by differentiating the horizontal drive pulse input to the second terminal 2 with the differentiating circuit 8 (the same applies hereafter in Figures 2 and 3) is applied to the 2D/FF in the IC3.
is applied to the pin as the T input of the first
Pulse b appearing at the collector of transistor Tr ₁
is divided by resistors R ₂₆ and R ₂₇ and becomes D of the second D/FF above.
Applied to the pin as an input. Therefore, the above
A pulse d is obtained at the pin of IC3 as the output of the second D/FF.

The pulse d from the pin is supplied to the charge/discharge control circuit 4.
The voltage is applied to the third transistor Tr ₃ in the transistor Tr 3 to turn on the transistor. When this third transistor is turned on, the aforementioned fourth transistor Tr ₄ is turned off, and therefore the charging/discharging capacitor C ₃ is connected to a variable resistor.
Discharge occurs via VR ₁ and resistor R ₉ , and the potential at point P decreases. Here, the pulse d falls after the end of the vertical synchronization pulse portion, and at this time the output voltage of the integrating circuit 7 has already decreased and the first transistor Tr ₁ is turned off (see waveform b). Therefore, even if the third transistor _Tr3 is turned off at the falling edge of the pulse d, the fourth transistor
Tr ₄ is still off and this fourth transistor
Tr ₄ is turned on again during the first pulse period of the vertical synchronizing pulse portion of the next field, as described above, and thereafter the same operation as before is repeated. Therefore, a periodic sawtooth wave voltage e appears for each field at point P.

Here, the phase relationship between the composite synchronization signal a and the leading edge differential pulse C of the horizontal drive pulse is as shown in Figure 2 for odd fields, and as shown in Figure 3 for even fields. , As can be seen from the above explanation, the charging periods Tc and Tc' of the charging/discharging capacitor _C3 in each of the above fields are as shown in the figure, and in the case of an odd field, it is 1/2H.
only becomes longer. Therefore, the peak of the sawtooth wave voltage e at point P is higher in the odd field, and exceeds the threshold level of the fifth transistor _Tr5 only during the peak period of the odd field. The fifth transistor is turned on. This allows the sixth and seventh transistors to
Since Tr ₆ and Tr ₇ are on during the above peak period, the seventh transistor is turned on only in odd fields.
A discrimination output pulse f (see Figures 2 and 3) is output to the collector of Tr ₇ , and this pulse f is output to the IC.
It is given to the pin as the set input (operates on the falling edge) of the 1st D/FF in 3.

On the other hand, when the first transistor Tr ₁ is on, the eighth transistor Tr ₈ in the pulse width conversion circuit 6
is also turned on, and the leading edge pulse of its collector output voltage is taken out by the differentiating circuit 6a and applied to the base of the ninth transistor _Tr9 , so that the pulse of FIG. 4g is obtained at this collector, This pulse g is applied to the pin of IC3 as the reset input (operates at the falling edge) of the first D.FF.
Therefore, the first D/FF operates as an RS flip-flop, and its Q output h and output i are output to pins and pins, respectively. As shown in the figure, these output pulses h and i have "high" and "low" inverted between odd and even fields,
These are used as field discrimination pulses.

The switching timing of the field discrimination pulses h and i between "high" and "low" is slightly delayed from the leading edge of the vertical synchronizing pulse, and is at the start of each field, that is, on the front side of the vertical synchronizing pulse. It does not exactly coincide with the beginning of the equivalent pulse. However, when the operation in the scanning period is switched by the discrimination pulses h and i, the above-mentioned slight deviation in the vertical blanking period does not cause any problem.

(g) Effects of the invention According to the invention, a field discrimination circuit can be realized at low cost with a very simple configuration, and is suitable for implementation in television receivers and the like.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing one embodiment of the present invention;
3, and 4 are signal waveform diagrams for explaining the operation. 3... IC for D flip-flop, 4... Charge/discharge control circuit, 5... Comparison detection circuit, 6... Pulse width conversion circuit, a... Composite synchronization signal, C'... Horizontal drive pulse.

Claims (1)

[Scope of utility model registration request] 2:1 interlaced scanning television composite synchronization signal; A second pulse generating circuit starts in synchronization with the horizontal driving pulse that first appears within the pulse period, and starts charging the charging/discharging capacitor at the timing of the leading edge of the first pulse. A field discrimination circuit includes a circuit that stops charging and starts discharging the charge/discharge capacitor at the leading edge timing, and a circuit that compares and detects the voltage of the capacitor with a constant voltage to obtain a discrimination output.