JPH0487100A - Dram - Google Patents

Abstract

PURPOSE:To facilitate the measurement of the leakage current of an insulated film by inhibiting the actuation of a sense amplifier despite the selection of a word line in a test mode, isolating the circuit which generates the value equal to the half of the power voltage, and keeping the paired bit lines equal to each other. CONSTITUTION:A clock signal TM 19 is set at a low level in a test mode and therefore a RAS signal, i.e., the basic signal of a DRAM is also set at a low level. Thus a selected word line W.L. 9W rises up and however the equalizing signal 8PSIEQ for bit lines 10 and 11 and the holding signal 7PSIHD are kept at high levels with the signal PSISA 16 kept at a low level respectively. In the circuits VBLGen 2 and VSGGen 4 which generates the value equal to the half of the power voltage respectively, both N type TR 17 and 18 are turned off and therefore both lines 10 and 11 and a cell plate of a memory cell become floating. Thus the leakage current of an insulated film can be easily measured with measurement of the current flowing between a VBL pad 3 and a VSG pad 5.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention has a memory cell consisting of one transistor and one capacitor, and further has a test mode function.
RAM (Dynamic Random Acc)
eseMemory).

[Conventional technology]

Generally, in a DRAM, one word line is provided for each row of memory cells in a memory cell array arranged in a matrix, and a bit line is provided for each column of memory cells.

FIG. 5 is a block diagram showing a part of a conventional general RAM, and here only peripheral circuits related to one memory cell are typically shown. In the figure, (1) is a memory cell array, (2) is a circuit that generates a level that is half the power supply voltage (hereinafter referred to as V!lLG an), (3
) is the vBL pad, (4) is the circuit that generates the % level of the power supply voltage (hereinafter referred to as V3GG, n), and (5) is the VS
a bad, (6) is sense amplifier, (7), (8)
, (16) is a signal, (9) is a word line, (10)
, Ht) are bit lines forming a bit line pair, (12
) to (14) are N-type transistors, and (15) is a capacitor.

Figure 6 shows the signal (7) ψHD and signal (8) in Figure 5.
) ψ8° is a block diagram showing a circuit that generates the RAS signal (36), and FIG. 7 shows the signal (16) in FIG. 5.
ψ! FIG. 3 is a block diagram showing a circuit that generates iA from word line (9) WL. In the figure, (35) is a bit line equalize hold signal generation circuit, and (34) is a sense amplifier activation signal generation circuit.

The memory cell array (1) has cells arranged in a matrix.
one N-type transistor (14) and one capacitor (1
5), and one memory cell includes a word line (9) W-L for selecting a memory cell in a specific row, a bit line (TO) connected to each memory cell, a bit line (11), and a bit line (10). , (11) are connected to a sense amplifier (6). The cell plate of capacitor (15) is V
Connected to 5GG-n (4). Bit line (10)
, (11), the bit line (1
0), (11) An N-type transistor (13) is provided to make the potentials the same, and the N-type transistor (1
3) is controlled by signal (8) ψEO. moreover,
In order to maintain the potential of the bit lines (10) and (11) at a level half of the power supply voltage during the non-operating period, an N-type transistor (1) controlled by the signal (7) ψHD is used.
2) Via VBLG! Connected to n(2).

The N-type transistor (14) constituting the memory cell is for connecting the bit line (10) (or (11)) and the capacitor (15), and is connected to the word line (9) W.
Controlled by L. The sense amplifier (6) receives the signal (1
6) ψSA activates the signal (16) ψSA
is generated using the word line (9) WL as a trigger. Also, signal (8) ψEQ + signal (7) ψHD are both DRA
It is generated using the RAS signal (36) which is the basis of M as a trigger. Furthermore, VBLG, , n(2) and v SG
The pads that serve to monitor the level of G an (4), namely VB Shibad (3) and VSG pad (
5) is often provided.

Next, the operation of the circuit shown in FIG. 5 will be explained using the timing chart shown in FIG.

First, when the RAS signal (36), which is a basic signal of DRAM, becomes Low, the signals (7), ψHD signal (8), and ψ6° sequentially become Low, and the bit line (10).

(11) and VSGGen (2) and VBLG-o (
4) are separated, and furthermore, the bit line of the bit line pair (
10) and (11) cancel equalization.

After that, a certain word line (9) W, L rises, and each N-type transistor (14) connected to that word line (9) W, L turns ONL, and the charge of the memory cell is transferred to the bit line (
10) and (11) are read out above. FIG. 8 shows a case where Low data is written in the memory cell. After that, the signal (16) that operates the sense amplifier (6)
) ψ0 is generated, amplifying the minute potentials of the bit lines (10) and (11) generated by the word lines (9) W and L. The level of v8 VSG is %Vcc.

[Problem to be solved by the invention]

Conventional DRAMs are configured as described above, so for example, if the insulating film of a certain memory cell capacitor is defective,
When a leak occurs, in order to measure the leak, set the word line that selects the leak cell to High level, do not operate the sense amplifier, equalize the bit line, and then set V BLG en, V SGG a
Disconnect n from the bit line and memory cell plate, and connect VB
Leakage between L pad and VsG pad must be measured. That is, there was a problem in that it was difficult to implement these methods.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a DRAM in which it is possible to easily measure insulating film leakage of defective memory cell capacitors.

[Means to solve the problem]

In the DRAM according to the present invention, the selected word line WL is set to H.
Even when the bit line pair reaches the high level, the bit line pair remains equalized and the sense amplifier does not operate, and furthermore, V s , G an and V 2 , LG an can be separated.

[Effect]

In this invention, in the test mode, even if the word line is selected, the sense amplifier is not operated and the V sGG
an and vBLGan are separated, and the bit line pair remains equalized.

(Example) Hereinafter, an example of the present invention will be explained with reference to the drawings.
The figure is a block diagram showing a peripheral circuit of one memory cell of a DRAM. In the figure, (1) to (16) are the same as those shown in the conventional example of FIG. 5, so their explanation will be omitted.

(17) and (18) are N-type transistors, (19
) is a clock signal. Bit line (10), (
11) VBLG-o to maintain the %VCC level
An N-type transistor (one) controlled by the clock signal (19) TM is inserted between (2) and the VBL pad (3) for monitoring the level of VBL, and
V 5 (IG en (4
) is inserted with an N-type transistor (18) controlled by a clock signal (19) TM.

FIG. 2 shows the signal (1) which is the sense activation signal shown in FIG.
6) A block diagram showing a circuit that generates ψSA by the word line (9) WL. Figure 3 shows the signal (8) ψ shown in Figure 1.
6°, signal (7) ψ) ID is a block diagram showing a circuit that generates the signal (7) ψ) ID using the RAS signal (36).

In the figure, (7), (s), (9), (16), and (19) are equivalent to those shown in FIG. (20), (23), (25)
, (28), (29).

(32) is an N-type transistor, (21), (22
).

(26), (27), (30), (
31) is a P-type transistor, (24), (33)
1 is a CMOS inverter, (34) is a sense amplifier activation signal generation circuit, and (35) is a bit line equalize hold signal generation circuit.

First, an N-type transistor (20) and a P-type transistor (21) are provided between the sense amplifier activation signal generation circuit (35) and the signal (16) ψ, and further between the signal (16) and GND. An N-type transistor (23) and a P-type transistor (22) are provided, and a clock signal TM is applied to each gate of the N-type transistor (20) and P-type transistor (22), and the P-type transistor (21) and the N-type transistor A clock signal (19) is connected to the gate of the transistor (23).
) TM CMOS inverter (24) The inverted signal from the next stage is input.

Next, FIG. 3 will be explained. An N-type transistor (25) and a P-type transistor (26) are connected between the bit line equalize hold signal generation circuit (35) and the signal (8) ψEQ.
) is inserted, the clock signal (19) TM is inserted into the gate of the N-type transistor (25), and the clock signal (19) TM is inserted into the gate of the P-type transistor (26).
An inverted signal of the clock signal (19) TM from one stage of the CMOS inverter (33) is input to the gate of the clock signal (19) TM.

Roughly VCC and signal (8) ψl:. A P-type transistor (27) and an N-type transistor (28) are inserted between them, and a clock signal (19) and an inverted signal are input to their respective gates, as described above.

Also, regarding signal (7) ψHD, the above signal (8) ψ
It is similar to EQ.

Next, the operation will be explained using FIG. 4.

First, when the device enters the test mode, the waveform becomes as shown by the solid line in the figure. In the test mode, the clock signal (19) TM becomes Low level.

Therefore, the RAS signal (36), which is the basic signal of DRAM,
When becomes Low, a selected word line (9) W, L rises, but the equalization signal (8) ψ5° and the hold signal (7) ψHD of the bit lines (10) and (11) both remain at High level. In addition, sense amplifier (6
) remains at Low level. Also v BLG an (2) and ■5G
Gen (4) is a bit line (10) because the N-type transistor (17) and N-type transistor (18) are turned off.

(11) and the cell plate of the memory cell becomes a floating state.

On the other hand, when not in test mode, the clock (19)T
Since M is at a high level, the same operation as in the prior art is possible, as shown by the waveform indicated by the broken line in FIG.

〔Effect of the invention〕

As described above, according to the present invention, certain word lines W, L,
is selected and goes to High level, the sense amplifier does not operate, and furthermore, V, LG sn and VSGG,
n, is separated from the bit line and cell plate, so even if a leak occurs in a certain memory cell insulating film,
By measuring the current between the vBL pad and the vso pad, there is an effect that the insulating film leakage current can be easily measured.

[Brief explanation of drawings]

1 to 3 show an embodiment of the present invention, in which FIG. 1 is a block diagram of a DRAM, and FIG. 2 shows a signal ψ shown in FIG. 1. FIG. 3 is a block diagram showing a circuit that generates the signals ψ6° and ψHD shown in FIG. 1 by the word line WL.
A block diagram showing a circuit in which is generated by the RAS signal,
FIG. 4 is a timing chart diagram showing signal waveforms of each part of the circuit in FIGS. 1 to 3, FIGS. 5 to 7 show conventional DRAMs, and FIG. 5 is a block diagram of the DRAM. Figure 6 shows the signal ψHD +ψEQ in Figure 5 as R.
Block diagram showing the circuit generated by the AS signal, No. 7
This figure is a block diagram showing a circuit that generates the signal ψSA from the word line WL in FIG. 5, and FIG. 8 is a timing chart showing signal waveforms at various parts of the circuits shown in FIGS. 5 to 7. In the figure, (1) is a memory cell array, (2) is a VB
LGel, (3) is VBL pad, (4) is Vg
GG6n, (5) is VSa bad, (6) is sense amplifier, (7), (8), (16) is signal, (1
9) is a clock signal, (9) is a word line, (24),
(33) is a CMOS inverter, (12),
(13), (14), (17), (
18). (20), (23), (25), (
28), (29). (32) is an N-type transistor, (21), (22
). (26), (27), (30), (
31) is a P-type transistor, (15) is a capacitor, (
10), (If) is a bit line, (34) is a sense amplifier activation signal generation circuit, (35) is a bit line equalize hold signal generation circuit, and (36) is a RAS signal. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] It has a plurality of memory cells each consisting of one transistor and one capacitor, and has a generation circuit that maintains the level of the bit line at half the power supply voltage during the non-operation period and further guarantees that level. In a semiconductor memory device having a generating circuit for making the cell plate potential half the power supply voltage, in the test mode, the bit line and the circuit generating half the power supply voltage are separated, and the cell plate and The circuit that generates the potential of A DRAM equipped with the ability to change to