JPH04878A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To make exposure time constant to all picture elements by applying a dot sequential readout resetting system and setting the gate line corresponding to shutter accumulating time to readout gate potential prior to readout operations. CONSTITUTION:This solid-state image pickup device is constituted in such a way that the gate impressing signal phiGm of the line to which resetting operations are performed for shuttering operations prior to readout is set to accumulating gate potential Vgs during picture element CMD readout time (t1, t2,...) and to readout potential Vgr during the resetting time (t1', t2',...) at every picture element following the readout operations. Accordingly, signals are obtained for one picture element only during a picture element CMD readout period and only a desired picture element corresponding to the shutter speed connected to the row line of the same row is reset during the resetting period of the picture element. Therefore, the exposure quantity is made constant to all picture elements and the difference in accumulating time can be eliminated.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a charge modulation element (Charge Modulation Element) which prevents accumulation time difference between each pixel.
The present invention relates to a solid-state imaging device with a shutter that uses an nDevice (hereinafter abbreviated as CMD) as a pixel.

[Conventional technology]

Conventionally, a CMD has been known as one of the light receiving elements having an MIS type light receiving/receiving integrated section and an internal amplification function.

In this CMD, a source region and a drain region are formed on the surface of a semiconductor layer so that a source/drain current flows parallel to the surface, and a gate is formed on the surface of the semiconductor layer between the source and drain regions via an insulating layer. It is configured with electrodes.

A solid-state imaging device has been proposed in which such CMDs are used as pixels and arranged in a matrix. There are three selection methods for pixel selection in this solid-state imaging device: drain-gate selection, source-gate selection, and source-drain selection.
The gate selection method is considered to be the most promising in terms of reducing the array area.

Regarding CMD solid-state imaging devices having a source follower readout configuration using a source/gate selection method, for example, Japanese Patent Laid-Open No. 61-136388 and Japanese Patent Laid-open No. 61-24567
In No. 7, the inventors of the present invention made a proposal,
Next, the configuration will be explained.

FIG. 4 is a circuit configuration diagram showing the above-mentioned proposed solid-state imaging device. CMDllll constituting each pixel, 11-
12. . . . 11-n are arranged in a matrix, and a video voltage Vee (>0) is commonly applied to each drain thereof. The gate terminals of the CMD groups in each row arranged in the X direction are connected to row lines 12-1, 12-2, . ...12-
The source terminals of the CMD groups arranged in the Y direction are connected to column lines 13-L, 13-2. = 6 column lines 13-1, 13-2, respectively connected to 43-n.・・・
. . . 13-n are column selection transistors 14, respectively.
-1.14-2.・・0.・14-n and anti-selection transistor 15-1.15-2. . . . Commonly connected to the video line 16 and the line 17 to which the voltage (≧O) is applied via the line 15-n. The video line 16 is grounded through a load resistor 18, and the load resistor 1
The signal is read out from the connection point between the video line 8 and the video line 16 via an output terminal 19.

Also, row line 12-1.12-2. ...12-
are connected to the vertical scanning circuit 20 and receive a signal φ, respectively. 3
．． φG8゜... φ axis is applied, column selection transistor 14-1゜14-2. ...14-n and anti-selection transistor 15-1゜15-2. ...1
The gate terminal of 5-n is connected to the horizontal scanning circuit 21,
Horizontal scanning signal φs1. φ3! .

...Apply φ37 and each inverted signal. Note that each CMD is formed on the same substrate, and a substrate voltage Vs-b+ (<0) is applied to the substrate.

FIG. 5 is a signal waveform diagram for explaining the operation of the solid-state imaging device shown in FIG.
．． ...Row selection gate application signal φ applied to 12-
G1+ φG11...φ. consists of a read gate voltage Ver with a small amplitude and a reset voltage ■ with a larger amplitude. During the scanning period tM of one row line, The horizontal blanking period t until horizontal scanning of the row line starts is set to a value of . Further, during the horizontal blanking period tmL, voltages near 1 and 1 are applied to row lines other than the readout row lines to suppress false signals, so that unnecessary holes are swept out to the substrate during readout. (Unexamined Japanese Patent Publication No. 6
1-136388) Also, column selection transistors 14-1, 14-2.・・・
...Horizontal scanning signal φ applied to the gate terminal of 14-n
8.

φ□18.・,・-3, is column line 13-1.13-
2. . . . 13-n; low level is a signal for selecting column selection transistors 14-1, 14-2, .・・・
...14-n is turned off, anti-selection transistor 15-1
．． 15-2. ...15-n is turned on, and the high level is set to a voltage value that turns on the column selection transistor and turns off the anti-selection transistor. The signal waveform diagram shown in FIG. 5 is when the voltage ■ applied to the line 17 is 0 volts, that is, when the line 17 is grounded.
When V>Q, the signal φ1+1+φG! ,...
In the waveform of φG, the reset voltages are increased in the positive direction.

Next, the operation of the solid-state imaging device configured as described above will be explained. By the operation of the vertical scanning circuit 2o, the signal φ
. 1 becomes the read gate voltage ■, r, row line 1
2-1 is connected to CMDll-11, 1112,...
...1l-1n is selected and the signal φ31. is output from the horizontal scanning circuit 21. φ3! , ...φS, the column selection transistors 14-1, 14-2. ...
...When 14-n is turned on sequentially, CMDII-11,1
The optical accumulation signals 1-12, . . . 11-111 are sequentially outputted from the output terminal I9 via the video line 16. Subsequently, this CMD group receives a signal φ. When 1 reaches the reset voltage ■0, the signal φ is reset all at once, and then the signal φ becomes ■1. Then, CMDII-11, 1142° . . . 1l-2n connected to the row line 12-2 is selected, and the signal φs1. φFuyi...φS.

CM D 11-11.11-12. ...
-The optical accumulation signals of -41-2n are sequentially read out and then reset all at once. Thereafter, the signals of each pixel are sequentially read out in the same manner, so that one field of video signal is obtained.

Next, the shutter operation will be explained. Figure 6 is a timing diagram of the row selection gate applied pulse signal to explain the shutter operation in this CMD solid-state imaging device.6 In normal shutter operation, in the case of frame accumulation in NTSC system operation, from 1730 seconds When it is desired to release a fast shutter, this can be achieved by performing a reset operation during the period (1/30 seconds) in which the relevant pixel is read. That is, the gate application signal φ@ll in FIG.
-Inφ. , the applied gate potential is raised to the reset voltage V1 during a desired horizontal blanking period (tML), and the pixels in the - row are reset all at once.

For example, in frame storage, if the gate row line 100 rows ahead is set to reset voltage ■ within the horizontal blanking period, the number of rows in the NTSC system is 488, so (1
/ 30) X (100/ 48B) z 1 /
A shutter operation with an exposure time of 150 seconds is possible.

[Problem to be solved by the invention]

By the way, in the shutter operation in the above-mentioned conventional CMD solid-state imaging device, the reset operation is performed in one row, so the accumulation time difference between pixels at both ends of the same row is determined by the number of horizontal scanning lines (in the CMD solid-state imaging device) in frame accumulation. (corresponding to the number of lines) is 500, (1/30) X
(1150G) 266 μsec.

During non-shutter operation, the accumulation time is 1/30 sec, so the accumulation time ratio of pixels at both ends of the same row is 99.8.
% and can be virtually ignored, but as the shutter speed increases, the difference in accumulation time between pixels at both ends becomes impossible to ignore.For example, 1/2000 seconds (= 500 u
sec), the exposure amount difference between the pixels at both ends is about 10%, and the accumulation time difference cannot be ignored.

The present invention has been made to solve the above-mentioned problems in conventional CMD solid-state imaging devices, and an object of the present invention is to provide a solid-state imaging device with a shutter that makes the exposure amount of all pixels constant and eliminates accumulation time differences. do.

[Means and effects for solving the problem] In order to solve the above problems, the present invention provides an array in which a large number of CMD pixels are arranged in a matrix, and each pixel in the array is sequentially selected by a source/gate selection method. In a solid-state imaging device, each pixel is reset by applying a negative potential greater than the storage gate potential and lower than a potential near the readout potential to the source column line after reading out each pixel. Prior to the readout operation of each pixel, the point-sequential readout reset means sets the potential applied to the gate row line corresponding to the shutter accumulation time to the readout potential during the point-sequential reset execution time by the point-sequential readout reset means, and The reading time other than the sequential reset execution time is configured by providing a shutter means to set the storage gate potential.

In the solid-state imaging device configured in this manner, the dot-sequential readout reset means performs a readout operation for each pixel and a reset operation for each pixel, and the shutter means resets a predetermined pixel by the dot-sequential readout and reset means. At the time when the operation is performed, a reset operation is performed for pixels connected to the column line of the predetermined pixel and to other gate row lines corresponding to the shutter accumulation time. As a result, a one-pixel readout, one-pixel reset method 〇〇MD solid-state imaging device with a shutter is achieved, and it is effectively possible to prevent exposure time differences from occurring for pixels in columns arranged in the same row.

〔Example〕

Prior to describing the embodiments, the dot sequential read reset method applied in the present invention will be described first.

As mentioned earlier, in conventional CMD solid-state imaging devices, the reset operation is performed for one row at a time, and the readout operation is performed for each pixel, so there is a difference in accumulation time between pixels in the same row and different column. . In principle, possible methods for eliminating such an accumulation time difference include a method in which both the reset operation and readout operation are performed in one row, and a method in which both the reset operation and readout operation are performed pixel by pixel.

Regarding the latter CMD solid-state imaging device that performs reset for each pixel applied in the present invention, for example,
No. 220674, proposed by the inventors of the present invention, and the circuit configuration diagram is shown in FIG. 1. This circuit configuration is almost the same as the conventional one shown in FIG. A variable source voltage pulse train v3 is applied by an on-chip circuit or an external circuit.

A drive signal waveform diagram for operating this CMD solid-state imaging device is shown in FIG. 2. The difference from the conventional drive signal waveform shown in FIG. 5 is the row selection gate application signal φ. 1.
...In φG, the gate pulse of the reset voltage vl for the reset operation during the horizontal blanking period is gone, and correspondingly, the source voltage pulse train ■3 is applied to reset each pixel. φ, φ1 . . , φ1 . φ8. are sequentially connected to the source column line selection transistors 14-1, 14-2 . ...14-
When applied to the gates of gates 1 and 7, gate voltages 1 and 7 are applied to the gate row lines (row lines 12-
The source currents of the CMD pixels connected to 1) are sequentially read out from the output terminal 19. The read time is the second
In the figure, the potential of the source voltage pulse train V is indicated by tI, 'tz, and t3, and the potential of the source voltage pulse train V at that time is Ov, as in the conventional one.

Immediately after one pixel is read out, the selection transistor 14-
1.14-2.・・・・・・! 4-n is in the on-layer state, then a negative voltage V1 is applied to the output terminal 19.
1 is applied. The value of the voltage VS+ is approximately the same as the read gate voltage (2), r, and is a potential in a more positive direction than the storage gate voltage. By applying this negative source voltage 1, the CMD at the read gate voltage
The pixel is in surface conduction mode and holes are swept out to the substrate. This operation resets only the CMD of one pixel in the row line to which the read gate voltage v1 is applied. The reset operation time is L+ + t2' +
It is indicated by t,'.

As described above, the point-sequential readout reset operation in the CMD solid-state imaging device is realized, but as described above, the present invention applies this point-sequential readout reset method to perform rows corresponding to the shutter accumulation time. The gate row line is set to a readout gate potential prior to a readout operation, so that the exposure time for all pixels becomes constant.

Next, an embodiment of the present invention will be explained.The circuit configuration of the present invention is the same as that of the dot sequential readout reset type solid-state imaging device shown in FIG. In FIG. 3, the row selection gate application signal φ@1. φG! , φG3, horizontal scanning signal -88, φs
z and the source voltage pulse train s are the same as those shown in Figure 2, and the difference from the drive signal waveform diagram shown in Figure 2 is the row line applied to the row line that is reset prior to reading. Selection gate application signal φ. , which forms the gate application pulse train.

That is, for the gate applied signal φ, , the pixel CM
During the readout time (1,,1!,...) of D, the storage gate potential is ■, s, and the reset time for each pixel following the readout operation (LI'+1!...)・・）
are formed to have read potentials v and r. By configuring the gate application signal φG1 of the row in which the reset operation is performed for the shutter operation prior to readout as described above, a signal for only one pixel can be obtained during the readout period of the pixel CMD, and the signal for only one pixel can be obtained. During the pixel reset period, only desired pixels corresponding to the shutter time connected to the same column line are reset.

This makes it possible to make the exposure amount of all pixels constant and eliminate accumulation time differences.

Although the above embodiments have been described using CMDs as pixels, the present invention can also be applied to solid-state imaging devices that use other amplification type light receiving elements such as SIT as pixels.

〔Effect of the invention〕

As described above based on the embodiments, according to the present invention, it is possible to realize a CMD solid-state imaging device with a shutter for one-pixel readout and one-pixel reset method, the exposure amount of all pixels is constant, and the accumulation time difference occurs. This problem can be solved.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram showing a configuration example of a solid-state imaging device using a point-sequential readout reset method applied in the present invention, FIG. 2 is a drive signal waveform diagram of the solid-state imaging device shown in FIG. 1, and FIG. 4 is a diagram showing a drive signal waveform of an embodiment of a solid-state imaging device according to the present invention, FIG. 4 is a circuit configuration diagram showing an example of the configuration of a conventional CMD solid-state imaging device, and FIG. The waveform diagram, FIG. 6, is a diagram showing the signal waveform for performing the shutter operation. In the figure, 11-11.11-12.・-41-an
is pixel CMDS12-1.12-2. ...12-
s is the row line, 13-1°13-2.・---・13
-n is the column line, 14-1.14-2.・、・14-n
is a column selection transistor, 15-1.15-2. ...
. . 15-n is an anti-selection transistor, 16 is a video line, 20 is a vertical scanning circuit, and 21 is a horizontal scanning circuit. Patent applicant: Olympus Optical Industry Co., Ltd. Figure 2 Figure 4 Vsub Vsub+ Figure 5 Figure 6

Claims (1)

[Claims] 1. A source region and a drain region are formed on the surface of the semiconductor layer so that a source/drain current flows in parallel to the surface, and a gate electrode is formed on the surface of the semiconductor layer between the source and drain regions via an insulating layer. A solid-state device comprising: an array in which the charge modulation element provided and configured is used as a pixel; a large number of the pixels are arranged in a matrix; and a scanning means for sequentially selecting each pixel of the array using a source/gate selection method and reading out an output signal. In an imaging device, a point-sequential readout reset means applies a negative potential greater than an accumulation gate potential and lower than a potential near the readout potential to a source column line after reading out each pixel to reset each pixel; Prior to operation, the potential applied to the gate row line corresponding to the shutter accumulation time is set to the readout potential during the point-sequential reset execution time by the point-sequential readout reset means, and the storage gate potential is set to the readout potential during the point-sequential reset execution time by the point-sequential reset execution time. A solid-state imaging device comprising a shutter means.