JPH048807B2 - - Google Patents

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Publication number
JPH048807B2
JPH048807B2 JP59257893A JP25789384A JPH048807B2 JP H048807 B2 JPH048807 B2 JP H048807B2 JP 59257893 A JP59257893 A JP 59257893A JP 25789384 A JP25789384 A JP 25789384A JP H048807 B2 JPH048807 B2 JP H048807B2
Authority
JP
Japan
Prior art keywords
power
signal
switch
contact
interrupt
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59257893A
Other languages
Japanese (ja)
Other versions
JPS61134824A (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP59257893A priority Critical patent/JPS61134824A/en
Publication of JPS61134824A publication Critical patent/JPS61134824A/en
Publication of JPH048807B2 publication Critical patent/JPH048807B2/ja
Granted legal-status Critical Current

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Description

【発明の詳細な説明】 〔産業上の利用分野〕 本願発明は計算機の処理装置がプログラムを実
行中に電源切断の割込処理を実施する場合の電源
切断制御方式に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a power-off control method when a computer processing device executes a power-off interrupt process while a program is being executed.

割込みによつて中断されるプログラムは、電源
切断時に実行再開に備えて予めデータが破断され
ないようフアイル等に退避させた後に供給電圧を
遮断する必要があるが、この切断処理の簡単で然
も迅速且つ確実な制御方式が望まれている。
When a program is interrupted by an interrupt, it is necessary to save the data to a file, etc. to prevent it from being destroyed before restarting execution when the power is turned off, and then cut off the supply voltage. Moreover, a reliable control method is desired.

〔従来の技術〕[Conventional technology]

従来例を図によつて説明する。第4図は従来例
を説明するブロツク図である。
A conventional example will be explained using figures. FIG. 4 is a block diagram illustrating a conventional example.

電源装置1は、処理装置2へ直流電圧Eを供給
するが、処理装置2の処理部3がプログラム4を
実行中に電源切断の割込みを実行する場合には、
実行中のデータDをフアイル装置5へ退避処理を
行つた後に、電源装置1の電源部6を切断する必
要ある。
The power supply device 1 supplies a DC voltage E to the processing device 2, but when the processing unit 3 of the processing device 2 executes a power-off interrupt while executing the program 4,
After the data D being executed is saved to the file device 5, it is necessary to disconnect the power supply section 6 of the power supply device 1.

従つて電源断の場合には、オペレーシヨンパネ
ル16の開閉スイツチの接点Sを閉じると、a点
の電位は0となり、これが割込信号1となつて割
込制御部7へ送出される。これにより割込制御部
7は、タイマ8を起動させると共に、割込み発生
を処理部3へ伝送する。処理部3は、プログラム
を実行中のときは、その実行を中止すると共に、
データDのフアイル装置5への退避を行い、然る
のちに制御部6に「電源断可」を通知する。これ
に伴い制御部6は、電源断コマンドBを電源装置
1へ送出する。該コマンドにより、例えば接点部
9の補助リレーを励磁し該リレーの接点で電源部
6のメインスイツチの励磁電流をカツトして入力
を切断し、二次電圧Eの供給を停止する。
Therefore, when the power is cut off, when the contact S of the open/close switch of the operation panel 16 is closed, the potential at point a becomes 0, and this becomes the interrupt signal 1 and is sent to the interrupt control section 7. As a result, the interrupt control unit 7 activates the timer 8 and transmits the occurrence of the interrupt to the processing unit 3. When the program is being executed, the processing unit 3 stops the execution, and
The data D is saved to the file device 5, and then the control unit 6 is notified that "power can be cut off". Along with this, the control unit 6 sends a power-off command B to the power supply device 1. In response to this command, for example, the auxiliary relay of the contact section 9 is energized, and the contact of the relay cuts off the excitation current of the main switch of the power supply section 6, cutting off the input and stopping the supply of the secondary voltage E.

なおこの過程において、実行中のプログラム4
がバグ等により暴走した場合には、プログラムの
実行中止、フアイル装置へのデータ退避等が出来
ないので、処理部3より制御部6へ「電源断可」
の信号が出ず電源切断は不可能となるが、タイマ
8から時間遅れをもつて出力信号Cが制御部6へ
送出され、制御部6から電源断コマンドBが電源
部へ送出され、強制的に電圧Eの供給が停止され
る。
In addition, in this process, the running program 4
If the program runs out of control due to a bug or the like, it will not be possible to stop the program execution or save data to the file device, so the processing unit 3 will send a message to the control unit 6 saying “power off”.
However, the timer 8 sends an output signal C to the control unit 6 with a time delay, and the control unit 6 sends a power-off command B to the power supply unit, making it impossible to turn off the power. The supply of voltage E is stopped at .

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

以上のように電源切断の割込処理時に何らかの
原因で実行中のプログラムが暴走した場合等、タ
イマを使用しなければ電源切断が出来ないという
問題点があつた。
As described above, there is a problem in that if the program being executed goes out of control for some reason during the power-off interrupt processing, the power cannot be turned off unless a timer is used.

〔問題点を解決するための手段〕[Means for solving problems]

上記の問題点は、接点の開閉により接点部に与
えられた電位が接地電位に変化する回路をもつた
スイツチを設け、該スイツチの操作により該接点
を開状態より閉状態にした時、前記電位変動によ
り、論理回路と、割込制御部を介して処理部に信
号を与え、該処理部は該信号によりプログラムの
実行を中止しデータをフアイル装置に退避せしめ
た電源切断指令を制御部に送出し、該制御部は前
記論理回路を介して電源切断信号を電源部に送出
して電圧供給を遮断せしめ、前記処理部より電源
切断指令が発生しない異常状態においても、前記
スイツチの接点が閉状態から開状態に復旧する時
点の前記電位変動による信号が論理回路に入力さ
れ、該論理回路より電源切断信号が電源部に送出
され電源供給を遮断せしめる手段を設けたことを
特徴とする電源切断制御方式によつて解決され
る。
The above problem is that a switch is provided with a circuit that changes the potential applied to the contact part to ground potential by opening and closing the contact, and when the contact is changed from the open state to the closed state by operating the switch, the potential applied to the contact part changes to the ground potential. Due to the fluctuation, a signal is given to the processing unit via the logic circuit and the interrupt control unit, and the processing unit uses the signal to send a power-off command to the control unit to stop the program execution and save the data to the file device. The control section sends a power cutoff signal to the power supply section via the logic circuit to cut off the voltage supply, and even in an abnormal state where a power cutoff command is not issued from the processing section, the contact of the switch remains closed. A power supply cutoff control characterized in that a signal due to the potential fluctuation at the time of restoration from the open state to the open state is inputted to a logic circuit, and the logic circuit sends a power supply cutoff signal to the power supply section to cut off the power supply. Solved by method.

〔作用〕[Effect]

以上のように本願発明は、プログラム実施中に
電源切断の割込処理をかける場合、プログラムが
暴走した状態でも、タイマを使用しなくても開閉
スイツチの操作後接点が閉から開へ復旧する状態
変化を利用して、電源装置を確実に切断せしめる
ことができる電源切断制御方式である。
As described above, the present invention provides a state in which when an interrupt process for power-off is performed during program execution, even if the program runs out of control, the contact returns from closed to open after operating the on/off switch without using a timer. This is a power-off control method that uses changes to reliably turn off the power supply.

〔実施例〕〔Example〕

以下、本願発明を図面によつて説明する。第1
図は本願発明の一実施例を説明するブロツク図、
第2図、第3図は本願発明の一実施例を説明する
タイムチヤートである。
Hereinafter, the present invention will be explained with reference to the drawings. 1st
The figure is a block diagram illustrating an embodiment of the present invention.
FIGS. 2 and 3 are time charts for explaining one embodiment of the present invention.

第1図において、オペレーシヨンパネル16の
スイツチ10は手で押下時は接点が閉となり手を
放すと自動復旧して開となる例えばノンロツクス
イツチである。スイツチ10の押下げにより接点
が閉になると、a点の電位は零電位となりフリツ
プフロツプ11がセツトされ、その出力端子Aの
信号レベルは1となる。その立ち上がり変化が、
割込信号Iとなつて割込制御部7へ送られ、同時
にNAND回路13に与えられる。
In FIG. 1, a switch 10 on an operation panel 16 is, for example, a non-locking switch, which closes its contacts when pressed by hand and automatically restores to open when released. When the contact is closed by pressing down the switch 10, the potential at point a becomes zero potential, the flip-flop 11 is set, and the signal level at its output terminal A becomes 1. The change in the rise is
The signal becomes an interrupt signal I and is sent to the interrupt control section 7, and is simultaneously applied to the NAND circuit 13.

割込制御部7は、この電源断の割込信号を処理
部3に送出し、処理部3はプログラム4の実行を
停止せしめ、データDをフアイル装置5へ退避し
た後電源切断指令を制御部に送出する。これによ
り制御部6は電源断信号bを出力し、NAND回
路12の入力レベルを反転し電源切断信号Mが出
力され、電源装置1の接点部9の補助リレーを駆
動して電源メインスイツチを切断し、電源部6か
らの電圧Eの供給が停止される。
The interrupt control unit 7 sends this power-off interrupt signal to the processing unit 3, and the processing unit 3 stops the execution of the program 4, saves the data D to the file device 5, and then sends the power-off command to the control unit. Send to. As a result, the control section 6 outputs the power-off signal b, inverts the input level of the NAND circuit 12, and outputs the power-off signal M, which drives the auxiliary relay of the contact section 9 of the power supply device 1 and disconnects the main power switch. However, the supply of voltage E from the power supply section 6 is stopped.

この制御動作の詳細を第2図のタイムチヤート
によつて説明する。
The details of this control operation will be explained with reference to the time chart of FIG.

第2図は、正常動作時のタイムチヤートであ
る。第2図において、aは時刻t1に、第1図にお
けるスイツチ10を押下げて接点を閉じ、時刻t4
に接点を開くと、該時刻t1〜t4の間の電位は0に
なる。またスイツチ10の接点が閉じると、時刻
t2にフリツプフロツプ11がセツトされ出力端子
Aのレベルは0から1に反転する。NAND回路
13の入力は1、0で出力は1となりNAND回
路12の入力は1、1で出力は0であり、該時刻
t2には電源には信号は送出されない。
FIG. 2 is a time chart during normal operation. In FIG. 2, at time t 1 , a pushes down the switch 10 in FIG. 1 to close the contact, and at time t 4
When the contact is opened at , the potential between times t 1 and t 4 becomes 0. Also, when the contact of switch 10 closes, the time
At t2 , flip-flop 11 is set and the level of output terminal A is inverted from 0 to 1. The inputs of the NAND circuit 13 are 1 and 0, and the output is 1, and the inputs of the NAND circuit 12 are 1 and 1, and the output is 0, and the time
No signal is sent to the power supply at t 2 .

第2図bはフリツプフロツプ11の出力端子A
の信号波形即ち割込信号Iの信号波形を示す。第
1図における処理部3が、cに示す如く時刻t3
割込みに対する応答信号Fを発すると、フリツプ
フロツプ11がリセツトされ、その出力端子Aの
信号レベルは、0に復帰する。従つてNAND回
路13の入力は0、0となり出力は1で、
NAND回路12の入力は1、1で出力は0に保
持され、時刻t3には電源装置1には信号は送出さ
れない。
FIG. 2b shows the output terminal A of the flip-flop 11.
The signal waveform of interrupt signal I, that is, the signal waveform of interrupt signal I is shown. When the processing section 3 in FIG. 1 issues a response signal F to the interrupt at time t3 as shown in c, the flip-flop 11 is reset and the signal level at its output terminal A returns to zero. Therefore, the inputs of the NAND circuit 13 are 0, 0, and the output is 1.
The inputs of the NAND circuit 12 are 1, 1, and the output is held at 0, and no signal is sent to the power supply device 1 at time t3 .

時刻t5に、処理部3によるプログラム4の実行
中止、データDのフアイル装置への退避が終了す
ると、この時点で処理部3は電源切断指令Gを制
御部6へ送出し、これにより制御部6は第2図d
に示す電源断信号bを出力する。これは図示の如
く負信号であるので、NAND回路12の入力は
0、1に変わり、出力は1となつて第2図eに示
すように電源切断信号Mが電源装置1へ送出さ
れ、第2図fに示す如く電源のメインスイツチを
切断し電源部6の供給電圧Eを遮断する。
At time t5 , when the processing unit 3 finishes executing the program 4 and saving the data D to the file device, the processing unit 3 sends a power-off command G to the control unit 6, which causes the control unit to 6 is Figure 2d
Outputs a power-off signal b shown in FIG. Since this is a negative signal as shown in the figure, the input of the NAND circuit 12 changes to 0 and 1, and the output becomes 1, and the power cut signal M is sent to the power supply device 1 as shown in FIG. As shown in FIG. 2(f), the main switch of the power source is turned off to cut off the supply voltage E of the power source section 6.

以上が正常動作の場合であるが、割込時にプロ
グラムの暴走等による異常動作の場合を、第1図
及び第3図によつて説明する。
The above is the case of normal operation, but the case of abnormal operation due to runaway of the program at the time of an interrupt will be explained with reference to FIGS. 1 and 3.

第1図において、スイツチ10を押下げると、
フリツプフロツプ11がセツトされ、その出力端
子Aの立上がりにより、信号Iが割込制御部7と
NAND回路の入力端子へ送られる。これにより
割込制御部7は、電源断の割込発生を処理部3へ
通知する。然るに、処理部3において実行中のプ
ログラムが暴走している場合には、処理部3から
は応答信号Fが発せられない。従つて制御部3か
らは電源断信号bも発せられない。これを第3図
のダイムチヤートで説明すると、第3図aの如く
時刻t1に第1図のスイツチ10の接点Sを閉じる
と、フリツプフロツプ11はセツトされ出力端子
Aは第3図bの如く時刻t2において1となり、
NAND回路13の入力は1、0で出力は1で、
従つてNAND回路12の入力は1、1で出力は
0に保たれ、この時点では電源に切断信号は出な
い。
In FIG. 1, when the switch 10 is pressed down,
The flip-flop 11 is set, and the rise of its output terminal A causes the signal I to be connected to the interrupt control section 7.
Sent to the input terminal of the NAND circuit. As a result, the interrupt control unit 7 notifies the processing unit 3 of the occurrence of a power-off interrupt. However, if the program being executed in the processing section 3 runs out of control, the processing section 3 will not issue the response signal F. Therefore, the control section 3 does not issue the power-off signal b either. To explain this using the dime chart in FIG. 3, when the contact S of the switch 10 in FIG. 1 is closed at time t1 as shown in FIG. becomes 1 at t 2 ,
The inputs of the NAND circuit 13 are 1 and 0, and the output is 1,
Therefore, the inputs of the NAND circuit 12 are kept at 1, 1, and the output is kept at 0, and no cutoff signal is issued to the power supply at this point.

然し、時刻t4の時点で、スイツチ10の押下げ
をやめ接点Sが復旧して間になると、NAND回
路13の入力は1、1となり該出力は第3図cの
如く0に反転し、NAND回路12の入力は1、
0で出力は1となり、第3図dに示される如く電
源切断信号Mが電源装置1へ送出され、リレー部
9の補助リレーを励磁し電源のメインスイツチを
切断するので、電源部6の供給電圧Eも第3図e
の如く遮断される。
However, at time t4 , when the switch 10 is no longer pressed and the contact S is restored, the input to the NAND circuit 13 becomes 1, 1, and the output is inverted to 0 as shown in Figure 3c. The input of the NAND circuit 12 is 1,
When the output is 0, the output becomes 1, and as shown in FIG. Voltage E is also Fig. 3 e
It is blocked like this.

以上のようにスイツチとしてノンロツクスイツ
チ等を使用すれば、復旧時のハネ返り信号を用い
ることにより電源切断することが出来る。
As described above, if a non-lock switch or the like is used as the switch, the power can be cut off by using the return signal at the time of restoration.

〔発明の効果〕〔Effect of the invention〕

本願発明により電源断の割込処理時にプログラ
ムの暴走等があつても、タイマを使用しなくても
簡単な制御方式で迅速、確実な電源切断の割込処
理が可能となつた。
According to the present invention, even if a program runs out of control during power-off interrupt processing, it is possible to quickly and reliably perform power-off interrupt processing using a simple control method without using a timer.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本願発明の一実施例を説明するブロツ
ク図、第2図、第3図は本願発明の一実施例を説
明するブロツク図、第4図は従来例を説明するブ
ロツク図、図において、1は電源装置、2は処理
装置、3は処理部、4はプログラム、5はフアイ
ル装置、6は制御部、7は割込制御部、8はタイ
マ、9は接点部、10はスイツチ、11はフリツ
プフロツプ、12,13はNAND回路、15は
ANDゲート、16はオペレーシヨンパネルを示
す。
FIG. 1 is a block diagram for explaining an embodiment of the present invention, FIGS. 2 and 3 are block diagrams for explaining an embodiment of the present invention, and FIG. 4 is a block diagram for explaining a conventional example. , 1 is a power supply device, 2 is a processing device, 3 is a processing section, 4 is a program, 5 is a file device, 6 is a control section, 7 is an interrupt control section, 8 is a timer, 9 is a contact section, 10 is a switch, 11 is a flip-flop, 12 and 13 are NAND circuits, and 15 is a flip-flop.
AND gate, 16 indicates the operation panel.

Claims (1)

【特許請求の範囲】 1 計算機の処理装置がプログラムを実行中に実
施する供給電圧遮断の割込処理による電源切断制
御方式において、 接点の開閉により接点部に与えられた電位が接
地電位に変化する回路をもつたスイツチを設け、
該スイツチの操作により該接点を開状態より閉状
態にした時、前記電位変動により、論理回路と、
割込制御部を介して処理部に信号を与え、該処理
部は該信号によりプログラムの実行を中止しデー
タをフアイル装置に退避せしめた後電源切断指令
を制御部に送出し、該制御部は前記論理回路を介
して電源切断信号を電源部に送出して電圧供給を
遮断せしめ、 前記処理部より電源切断指令が発生しない異常
状態においても、前記スイツチの接点が閉状態か
ら開状態に復旧する時点の前記電位変動による信
号が論理回路に入力され、該論理回路より電源切
断信号が電源部に送出され電源供給を遮断せしめ
る手段を設けたことを特徴とする電源切断制御方
式。
[Scope of Claims] 1. In a power cutoff control method using interrupt processing for supply voltage cutoff, which is executed by a processing unit of a computer while a program is being executed, the potential applied to the contact part changes to the ground potential by opening and closing of the contact. A switch with a circuit is provided,
When the contact is changed from an open state to a closed state by operating the switch, the logic circuit and
A signal is given to the processing section via the interrupt control section, and the processing section stops the execution of the program in response to the signal, saves the data to the file device, and then sends a power-off command to the control section. A power-off signal is sent to the power supply unit via the logic circuit to cut off the voltage supply, and even in an abnormal state where a power-off command is not issued from the processing unit, the contact of the switch is restored from the closed state to the open state. A power cut-off control method, characterized in that a signal based on the potential fluctuation at a point in time is inputted to a logic circuit, and a power cut-off signal is sent from the logic circuit to a power supply section to cut off the power supply.
JP59257893A 1984-12-06 1984-12-06 Cut-off control system of power supply Granted JPS61134824A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59257893A JPS61134824A (en) 1984-12-06 1984-12-06 Cut-off control system of power supply

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59257893A JPS61134824A (en) 1984-12-06 1984-12-06 Cut-off control system of power supply

Publications (2)

Publication Number Publication Date
JPS61134824A JPS61134824A (en) 1986-06-21
JPH048807B2 true JPH048807B2 (en) 1992-02-18

Family

ID=17312648

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59257893A Granted JPS61134824A (en) 1984-12-06 1984-12-06 Cut-off control system of power supply

Country Status (1)

Country Link
JP (1) JPS61134824A (en)

Also Published As

Publication number Publication date
JPS61134824A (en) 1986-06-21

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