JPH04881A - Fault and sensitivity correction device for two-dimensional array type infrared video camera - Google Patents
Fault and sensitivity correction device for two-dimensional array type infrared video cameraInfo
- Publication number
- JPH04881A JPH04881A JP2101249A JP10124990A JPH04881A JP H04881 A JPH04881 A JP H04881A JP 2101249 A JP2101249 A JP 2101249A JP 10124990 A JP10124990 A JP 10124990A JP H04881 A JPH04881 A JP H04881A
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- JP
- Japan
- Prior art keywords
- data
- ram
- rom
- camera
- sensitivity correction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Closed-Circuit Television Systems (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、二次元アレイ型赤外線ビデオカメラの欠陥画
素の補償と感度の画面内均−化のための補正に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to compensation for defective pixels in a two-dimensional array type infrared video camera and correction for equalizing sensitivity within the screen.
従来の二次元アレイ型赤外ビデオカメラの欠陥画素に対
する補償と、検出器への均一な入射に対して均一な画面
出力を得るための感度補正の方法の1例を第3図に示す
。FIG. 3 shows an example of a sensitivity correction method for compensating for defective pixels in a conventional two-dimensional array type infrared video camera and for obtaining a uniform screen output for uniform incidence on the detector.
(1)は二次元アレイ型の赤外線検出器、(2)は第1
のROM、 (3)は第2のROM、 (4)はA/D
コンバータ、(6)は欠陥補正回路、(8)は感度補正
回路、 (11)は赤外検出器からのアナログ出力信号
、 (12)はA/Dコンバータによって変換されたデ
ィジタル出力信号、 (13)は欠陥画素補正されたデ
ィジタル出力信号、 (14)は感度補正を完了した最
終ディジタル出力信号である。(1) is a two-dimensional array type infrared detector, (2) is the first
ROM, (3) is second ROM, (4) is A/D
converter, (6) is a defect correction circuit, (8) is a sensitivity correction circuit, (11) is an analog output signal from an infrared detector, (12) is a digital output signal converted by an A/D converter, (13) ) is the digital output signal after defective pixel correction, and (14) is the final digital output signal after sensitivity correction has been completed.
赤外線検出器(1)と、前記検出器(1)から出力され
たアナログ信号(11)をディジタルデータ(12)に
変換するA/Dコンバータ(4)と、欠陥画素のアドレ
スデータを記憶させた第1のROM (2)と。An infrared detector (1), an A/D converter (4) that converts the analog signal (11) output from the detector (1) into digital data (12), and address data of the defective pixel is stored. and a first ROM (2).
感度の不均一性を補う感度補正データを記憶させた第2
のROM (3)と1例えば、欠陥画素に対して第4図
に示すようなフリップフロップを使ったラッチ回路によ
って、欠陥画素を1つ前の正常な画素と同一のデータで
埋め合わせをするような欠陥補正回路(6)と9例えば
1乗算回路による各画素毎の感度補正回路から成り、最
終的に欠陥補正と感度補正がなされたディジタル信号を
得る。The second one stores sensitivity correction data that compensates for sensitivity non-uniformity.
ROM (3) and 1 For example, a latch circuit using a flip-flop as shown in Figure 4 is used to compensate for a defective pixel with the same data as the previous normal pixel. It consists of a defect correction circuit (6) and a sensitivity correction circuit for each pixel (9), for example, one multiplication circuit, and finally obtains a digital signal that has been subjected to defect correction and sensitivity correction.
前記のようなカメラでは、カメラヘッドと欠陥および感
度補正データを搭載したカメラコントローラは分離され
ているため、カメラヘッドとカメラコントローラが常に
一対一で対応している必要があり、同一機種であっても
カメラヘッドあるいはカメラコントローラは互換性を得
られないという難点があった。In the above-mentioned cameras, the camera head and the camera controller equipped with defect and sensitivity correction data are separated, so the camera head and camera controller must always correspond on a one-to-one basis, even if they are of the same model. However, the problem was that the camera heads or camera controllers were not compatible.
本発明は、このような難点を解決するためになされたも
ので、何らかの事由によりカメラヘッドあるいはカメラ
コントローラに交換の必要が生しても、欠陥および感度
補正に支障がないように互換性がある装置とする事を目
的としている。The present invention was made to solve these difficulties, and even if the camera head or camera controller needs to be replaced for some reason, it is compatible so that defects and sensitivity correction will not be affected. It is intended to be used as a device.
欠陥画素アドレスデータを記憶させた第1のROMと、
感度補正データを記憶させた第2のROMとをカメラヘ
ッドに搭載し、これらのメモリの内容をカメラヘッドか
らカメラコントローラに転送できるようにカメラヘッド
に送信器、カメラコントローラに受信器を搭載し、欠陥
補正のための回路と、感度補正のための回路とをカメラ
コントローラに搭載し、カメラコントローラで補正処理
ができるよう、上記第1のROMの内容を収納する第1
のRAMと、上記第2のROMの内容を収納する第2の
RAMとをカメラコントローラに搭載する。a first ROM storing defective pixel address data;
A second ROM storing sensitivity correction data is mounted on the camera head, and a transmitter is mounted on the camera head and a receiver is mounted on the camera controller so that the contents of these memories can be transferred from the camera head to the camera controller. A circuit for defect correction and a circuit for sensitivity correction are installed in the camera controller, and the first ROM stores the contents of the first ROM so that the camera controller can perform correction processing.
and a second RAM that stores the contents of the second ROM are installed in the camera controller.
これによって、カメラヘッドが他のカメラヘッドと交換
されても、あるいはカメラコントローラが池のカメラコ
ントローラと交換されても、適切な補正がなされる事に
なる。As a result, even if the camera head is replaced with another camera head or the camera controller is replaced with another camera controller, appropriate corrections will be made.
さらに、感度補正データのうちのある特定のデータを欠
陥画素を示すデータとし、カメラコントローラに上記の
欠陥画素を示すある特定のデータを識別するためのデコ
ーダを搭載する事で、上記第1のROMと第1のRAM
を削減するようにしたものである。Furthermore, by using certain data of the sensitivity correction data as data indicating a defective pixel, and installing a decoder for identifying the certain specific data indicating the defective pixel in the camera controller, the first ROM and the first RAM
It was designed to reduce the
〔作用〕
本発明は、カメラヘッド毎に異なる補正データをカメラ
ヘッドのROMに搭載し、これらのROMの内容をカメ
ラコントロール側のRAMへ転送できるようにしたため
、カメラヘッドあるいはカメラコントローラの互換性を
可能にした。[Function] In the present invention, different correction data for each camera head is loaded into the ROM of the camera head, and the contents of these ROMs can be transferred to the RAM on the camera control side, thereby improving the compatibility of the camera head or camera controller. made possible.
第1図にその実施例を示す。第1のROM (2)から
送信器(9)、受信器(10)を介して転送されて来た
欠陥アドレスデータが収納される第1のRAM(5)と
、第2のROM (3)から、送信器(9)。An example is shown in FIG. A first RAM (5) that stores defective address data transferred from the first ROM (2) via the transmitter (9) and receiver (10), and a second ROM (3). From, the transmitter (9).
受信器(10)を介して転送されて来た感度補正データ
が収納される第2のRAM(7)によって、カメラヘッ
ドあるいはカメラコントローラは互換性をもつ事ができ
る。A second RAM (7) in which the sensitivity correction data transferred via the receiver (10) is stored allows the camera head or camera controller to be compatible.
すなわち、第1のRA M (5)に第1のROM(2
)の内容か、第2のRA M (7)に第2のROM(
3)の内容が転送される事によって、あたかも第1゜第
2のROMがカメラコントローラに搭載されているが如
くなり、第1のRAM(5)の欠陥画素アドレスデータ
は各画素毎に、ラッチ回路(6)に送られ、ここで、欠
陥補償処理が施される。正常画素は何らの処理も受けず
にラッチ回路(6)から出力される。さらに第2のRA
M(7)から画素毎に感度補正データが出力され乗算回
路(8)で、ラッチ回路から出力された信号(13)と
乗算され、感度補正されたディジタル出力信号(14)
となる。That is, the first RAM (5) is connected to the first ROM (2).
), the contents of the second RAM (7) are stored in the second ROM (
By transferring the contents of 3), it becomes as if the first and second ROMs are installed in the camera controller, and the defective pixel address data in the first RAM (5) is stored in the latch for each pixel. It is sent to the circuit (6), where it undergoes defect compensation processing. Normal pixels are output from the latch circuit (6) without undergoing any processing. Furthermore, a second RA
Sensitivity correction data is output from M (7) for each pixel, and multiplied by the signal (13) output from the latch circuit in a multiplier circuit (8) to produce a sensitivity-corrected digital output signal (14).
becomes.
ところで、欠陥画素アドレスデータは、各画素に対して
欠陥であるか正常であるかを識別するため1ビツトのデ
ータであり、一方、感度補正データの欠陥画素に相当す
るデータは感度補正に対しては必要のないデータになっ
ているので、この感度補正データの欠陥画素相当のデー
タには欠陥画素である事を示すための、先め定められた
識別コードを与え、メモリを1つのメモリとする事も可
能である。例えば、感度補正階調が256階調である時
、このうちの1階調分のデータ、例えば全ビットが1ま
たは全ピッ−が0であるようなデータを欠陥画素の識別
コードとして設定すれば、感度補正階調は255階調に
減るが、メモリが1つ削減できるというメリットが出る
。By the way, the defective pixel address data is 1-bit data for identifying whether each pixel is defective or normal.On the other hand, the data corresponding to the defective pixel in the sensitivity correction data is used for sensitivity correction. is unnecessary data, so the data corresponding to the defective pixel in this sensitivity correction data is given a predetermined identification code to indicate that it is a defective pixel, and the memory is made into one memory. It is also possible. For example, when the sensitivity correction gradation is 256 gradations, data for one gradation, for example, data in which all bits are 1 or all pips are 0, can be set as the defective pixel identification code. , the number of sensitivity correction gradations is reduced to 255 gradations, but the advantage is that the number of memories can be reduced by one.
第2図はこの実施例を示す。欠陥画素を示すコードと感
度補正データが記録されているR A M (5)から
の感圧データと、A/Dコンバータからの出力ディジタ
ル信号(12)は乗算回路(8)で乗算され。FIG. 2 shows this embodiment. The pressure sensitive data from the RAM (5), in which the code indicating the defective pixel and the sensitivity correction data are recorded, and the output digital signal (12) from the A/D converter are multiplied by the multiplier circuit (8).
RAMからのデータはデコーダ(15)で当該データが
欠陥画素を示すデータコードであるか、正常な画素に対
する感度補正データであるのかが識別される。欠陥画素
を示すデータであると判断されるとラッチ回路(6)の
イネーブル端子ヘラッチイネーブル信号か送られ感度補
正済み信号(13)に対してラッチ回路(6)によって
1例えば、当該画素のデータを1つ前の画素データに置
き換える処理が施され、欠陥および感度補正済みのディ
ジタル信号(14)が出力される。The data from the RAM is identified by a decoder (15) as to whether the data is a data code indicating a defective pixel or sensitivity correction data for a normal pixel. When it is determined that the data indicates a defective pixel, a latch enable signal is sent to the enable terminal of the latch circuit (6), and the latch circuit (6) outputs 1, for example, the data of the pixel in response to the sensitivity corrected signal (13). is replaced with the previous pixel data, and a defect and sensitivity corrected digital signal (14) is output.
本発明は9以上説明した通り、カメラヘッドが異なって
も、あるいはカメラコントローラカ異なっても当該検出
器に対応した欠陥画素データと感度補正データがROM
に記録されカメラヘッドに搭載されており、これらのデ
ータをカメラコントローラに搭載しであるRAMに転送
するため、補正がカメラコントローラで実行され1機器
の間で互換性の保持が可能となる効果がある。As explained above, even if the camera head or camera controller is different, the defective pixel data and sensitivity correction data corresponding to the detector are stored in the ROM.
This data is stored in the camera head and transferred to the RAM in the camera controller, so corrections are executed in the camera controller, making it possible to maintain compatibility between devices. be.
第1図及び第2図は本発明の実施例を示す図。
第3図は従来の欠陥及び感度補正装置の構成を示す図、
第4図は欠陥画素補償のラッチ回路を示す図であり、(
1)は赤外線検出器、(2)は第1のROM、(3)は
第2のROM、 (4)はA/Dコンバータ、(5)は
第1のRAM、(6)はラッチ回路。
(7)は第2のRAM、 (8)は乗算回路、(9)は
送信器、 (10)は受信器、 (11)は無補正の赤
外ビデオ信号、 (12)はディジタルビデオ信号、
(13)は欠陥補償ディジタルビデオ信号、 (14)
は欠陥・感度補正済みディジタルビデオ信号、 (15
)はデコーダ。
(16)はディジタルビデオ信号、 (17)はクロッ
ク信号、 (18)はROMデータ、 (19)はラッ
チイネーブル端子である。
なお9図中同一あるいは相当部分には同一符号を付しで
ある。FIGS. 1 and 2 are diagrams showing embodiments of the present invention. FIG. 3 is a diagram showing the configuration of a conventional defect and sensitivity correction device;
FIG. 4 is a diagram showing a latch circuit for defective pixel compensation.
1) is an infrared detector, (2) is a first ROM, (3) is a second ROM, (4) is an A/D converter, (5) is a first RAM, and (6) is a latch circuit. (7) is the second RAM, (8) is the multiplication circuit, (9) is the transmitter, (10) is the receiver, (11) is the uncorrected infrared video signal, (12) is the digital video signal,
(13) is a defect-compensated digital video signal, (14)
is a defect/sensitivity corrected digital video signal, (15
) is a decoder. (16) is a digital video signal, (17) is a clock signal, (18) is ROM data, and (19) is a latch enable terminal. Note that the same or corresponding parts in FIG. 9 are given the same reference numerals.
Claims (2)
アレイ型赤外ビデオカメラ用欠陥および感度補正装置に
おいて、カメラヘッド内に置かれる赤外線検出器の欠陥
画素アドレスを記憶させた第1のROMと、カメラヘッ
ド内に置かれる赤外線検出器の画素毎の感度補正データ
を記憶させた第2のROMと、上記カメラヘッド内に置
かれ、上記第1、第2のROMのデータを上記カメラコ
ントローラに送信する回路と、上記カメラコントローラ
に置かれ、上記の送信データを受信する回路と、上記第
1のROMの内容を収納する第1のRAMと、上記第2
のROMの内容を収納する第2のRAMと、赤外線検出
器のアナログ電圧をディジタル信号に変換するA/D変
換器と、第1のRAMからのデータがイネーブル端子に
接続され、上記A/D変換器からのディジタル信号が入
力端子に接続されているラッチ回路と、第2のRAMか
らのデータとラッチ回路からの出力データが乗算される
ように接続されている乗算回路とを備えたことを特徴と
する二次元アレイ型赤外ビデオカメラ用欠陥および感度
補正装置。(1) In a defect and sensitivity correction device for a secondary array type infrared video camera consisting of a camera head and a camera controller, a first ROM that stores a defective pixel address of an infrared detector placed in the camera head, and a camera a second ROM that stores sensitivity correction data for each pixel of an infrared detector placed in the head; and a second ROM placed in the camera head that transmits data in the first and second ROMs to the camera controller. a circuit, a circuit placed in the camera controller and receiving the transmission data, a first RAM storing the contents of the first ROM, and a second RAM.
A second RAM that stores the contents of the ROM, an A/D converter that converts the analog voltage of the infrared detector into a digital signal, and data from the first RAM are connected to an enable terminal, and the A/D The present invention includes a latch circuit to which the digital signal from the converter is connected to an input terminal, and a multiplier circuit connected to multiply the data from the second RAM and the output data from the latch circuit. Features: Defect and sensitivity correction device for two-dimensional array type infrared video camera.
元アレイ型赤外ビデオカメラ用欠陥および感度補正装置
において、カメラヘッドに搭載させる欠陥画素アドレス
データと感度補正データを記憶させたROMと、上記カ
メラヘッド内に置かれ上記ROMのデータを上記カメラ
コントローラへ送信する回路と、上記カメラコントロー
ラに置かれ上記送信回路から送信された上記ROMデー
タを受信する回路と、受信したROMデータを収納する
RAMと、上記RAMからある特定のデータを識別する
デコーダと、赤外線検出器のアナログ出力電圧をディジ
タル信号に変換するA/D変換器と、RAMからのデー
タとA/D変換器からのディジタル信号が乗算されるよ
う接続された乗算器とRAMと接続されたデコーダと、
デコーダの出力がイネーブル端子に、上記乗算器の出力
がデータ入力端子にそれぞれ接続されたラッチ回路とを
備えたことを特徴とする二次元アレイ型赤外ビデオカメ
ラ用欠陥および感度補正装置。(2) In a defect and sensitivity correction device for a two-dimensional array infrared video camera consisting of a camera head and a camera controller, a ROM that stores defective pixel address data and sensitivity correction data to be mounted on the camera head, and a ROM inside the camera head. a circuit placed in the camera controller for transmitting the ROM data to the camera controller; a circuit placed in the camera controller for receiving the ROM data transmitted from the transmission circuit; a RAM for storing the received ROM data; A decoder that identifies certain data from the RAM, an A/D converter that converts the analog output voltage of the infrared detector into a digital signal, and the data from the RAM and the digital signal from the A/D converter are multiplied. a multiplier connected to the RAM and a decoder connected to the RAM;
A defect and sensitivity correction device for a two-dimensional array type infrared video camera, comprising a latch circuit in which the output of the decoder is connected to an enable terminal, and the output of the multiplier is connected to a data input terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2101249A JP2605448B2 (en) | 1990-04-17 | 1990-04-17 | Defect and sensitivity correction device for two-dimensional array type infrared video camera |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2101249A JP2605448B2 (en) | 1990-04-17 | 1990-04-17 | Defect and sensitivity correction device for two-dimensional array type infrared video camera |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04881A true JPH04881A (en) | 1992-01-06 |
| JP2605448B2 JP2605448B2 (en) | 1997-04-30 |
Family
ID=14295636
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2101249A Expired - Lifetime JP2605448B2 (en) | 1990-04-17 | 1990-04-17 | Defect and sensitivity correction device for two-dimensional array type infrared video camera |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2605448B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007158627A (en) * | 2005-12-02 | 2007-06-21 | Sumitomo Electric Ind Ltd | Infrared light imaging apparatus, signal processing apparatus, and infrared light imaging method |
| EP3503046A1 (en) * | 2017-12-22 | 2019-06-26 | CI Tech Sensors AG | System comprising a processing device and a connected camera, for detecting of a machine-readable security feature of a valuable document and method for exchanging a camera in such a system |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5621485A (en) * | 1979-07-30 | 1981-02-27 | Fujitsu Ltd | Signal processing method of infrared-rays image pickup device |
| JPS62169573U (en) * | 1986-04-16 | 1987-10-27 |
-
1990
- 1990-04-17 JP JP2101249A patent/JP2605448B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5621485A (en) * | 1979-07-30 | 1981-02-27 | Fujitsu Ltd | Signal processing method of infrared-rays image pickup device |
| JPS62169573U (en) * | 1986-04-16 | 1987-10-27 |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007158627A (en) * | 2005-12-02 | 2007-06-21 | Sumitomo Electric Ind Ltd | Infrared light imaging apparatus, signal processing apparatus, and infrared light imaging method |
| EP3503046A1 (en) * | 2017-12-22 | 2019-06-26 | CI Tech Sensors AG | System comprising a processing device and a connected camera, for detecting of a machine-readable security feature of a valuable document and method for exchanging a camera in such a system |
| CN109961554A (en) * | 2017-12-22 | 2019-07-02 | Ci技术传感器公司 | The method of system and the camera for replacing this system with processing unit and the camera being attached to |
| US10560691B2 (en) | 2017-12-22 | 2020-02-11 | CI Tech Sensors, AG | System, having a processing device and a camera connected thereto. for the detection of a machine-readable security feature of a value document and method for exchanging a camera of such a system |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2605448B2 (en) | 1997-04-30 |
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