JPH0488434A - Data processor - Google Patents

Abstract

PURPOSE:To recover an error at a high speed without reloading to the entirety in the case of intermittent trouble due to malfunction, etc., by rewriting a word where an error occurs in a RAM used exclusively for reading with initially loaded data. CONSTITUTION:When trouble occurs to the read-only RAM 1, a read data register 3 makes a parity check to detect an error and the operation of the device which uses the read-only RAM 1 is stopped. At this time, the error address is held in an error address register 9, the detected error is reported to a trouble processor 5, and the error address in the error address register 9 and the error data in a read data register 3 are inputted. Then the error address is used as the address of a loaded data storage means 6 to obtain corresponding data, which is used to send a write indication to the read-only RAM 1, thereby indicating restart actuation to the device. Consequently, an excessive temporary stop due to the operation stop or reloading of the device in the case of the trouble becomes unnecessary.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a data processing device, and particularly to a read-only RA.
The present invention relates to a data processing device having M.

[Conventional technology]

Conventionally, in this type of data device, when a failure occurs in the read-only RAM, the error is automatically corrected using an error correction code, or the device operation is stopped and the device is restarted to recover. The initial microprogram load was used to reload and resume operation.

[Problem to be solved by the invention]

The above-mentioned conventional data processing apparatus has the disadvantage that the delay time of the error correction circuit cannot be ignored and the delay time of the error correction circuit cannot be ignored as the speed of the apparatus increases, so that the apparatus having an error correction code cannot be adopted or the speed cannot be increased.

Devices that do not employ error correction codes have the disadvantage that they require a large amount of temporary suspension by stopping or reloading the device. Furthermore, when such a failure occurs, there is a drawback that although the error address of the read-only RAM can be determined, it is not possible to determine which bit has caused the error.

[Means to solve the problem]

The data processing device of the present invention includes a read-only RAM loaded from an external storage device by initial microprogram loading, a read data register that latches data read from the RAM and performs a parity check, and a read address and an address register for holding a write address; a one-word writable write data register for the RAM; a load data storage means for storing a copy of the load data in the RAM that is loaded at the same time as the initial microprogram load; When an error is detected in the data register, the error address held in the address register is retrieved, the data corresponding to this error address is read from the load data storage means, and the data is read into the RAM using the write data register. and a fault handling device that rewrites the data.

Further, the data processing device of the present invention may be arranged such that the data processing device corresponds to the error address which is the content of the address register when an error is detected in the read data register, and the error data and the error address which are the contents of the read data register. The apparatus may include a failure information storage means for storing the contents of the load data storage means as failure information, and a means for pointing out a failure location based on the contents of the failure information.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

Read-only RAMI is loaded with microprograms, etc. during initial setup of the device, and is normally read only.
AM, and the data of the word specified by the address register 4 is read to the read register 3. Although normal operation is not shown in the figure, the read data is supplied from the read register 3 to each section. Also,
The read register 3 performs a parity check on the read data, and if an error is detected, stops the operation and notifies the failure processing device 5. The error address register 9 holds the address at which the error was detected in the read data register 3, and is connected to the fault processing device 5 together with the read register 3 so that it can be taken out as fault information. Write data register 2 is read-only R
Used for initial loading of AM 1, read-only RA
Used for writing M1. The load data storage means 6 is a memory in which the same data as the load data of the read-only RAM 1 is stored, and is stored at the time of initial loading.

The service processor 7 is a processor that stores the fault information notified from the fault processing device f5 into the fault information storage means 8 or outputs it to an output device such as a printer.

Next, the operation of the present invention will be explained with reference to the drawings.

If a failure occurs in the read-only RAM 1, a parity check is performed in the read data register 3 and an error is detected. Read-only R, A when an error is detected
Stop the operation of the device using M1. If the read-only RAM 1 stores a microprogram, the operation of the microprogram is stopped. The error address at that time is held in the error address register 9. The detected error is notified to the fault processing device 5, and the fault processing device 5 takes in the error address in the error address register 9 and the error data in the read data register 3. The error address is used as the address of the load data storage means 6, and data corresponding to this error address is obtained. The obtained data is written into the write data register 2.
It also sets the error address in the address register 4, issues a write instruction to the read-only RAM 1, and instructs the device using the read-only RAM 1 to restart.

In this way, the error in the read-only RAM 1 is recovered. Therefore, if the current failure is an intermittent failure such as a malfunction, the operation can be continued as is. If this function is not provided, it will not be possible to recover from the error even if it occurs intermittently, and the error will always recur, making it impossible to continue operation.

On the other hand, the error address and error data collected as failure information are notified to the service processor 7 along with the data corresponding to the error address read from the load data storage means 6, that is, the correct value of the erroneous data. The service processor 7 stores the fault information in the fault information storage means 8 along with additional information such as the time of occurrence. At this time, the exclusive OR of the error data and correct data is performed to find out which bit caused the error. As a result, the physical location involved in the error occurrence,
The object is pointed out and stored in the fault information storage means 8 together with the fault information described above.

〔Effect of the invention〕

As explained above, the present invention is capable of quickly recovering from an error without having to reload the entire memory in the event of an intermittent failure due to malfunction, etc. by rewriting the word in which an error has occurred in a RAM used for read-only with initial load data. It has the effect of being able to.

In addition, by saving the data used for rewriting, that is, the correct data, along with the error address and error data as fault information, and by making it possible to identify the fault location (bit) from these data, save it, and output it.
This has the effect that fault search can be performed automatically.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. 1... Read-only RAM, 2... Write data register, 3... Read data register, 411.
Address register, 5... Failure processing device, 6... Load data storage means, 7... Service processor, 8
. . . Failure information storage means, 9 . . . Error address register.

Claims (1)

[Claims] 1. A read-only RAM loaded from an external storage device by initial microprogram loading, and this RAM
a read data register that latches data read from and performs a parity check; an address register that holds read addresses and write addresses;
a one-word writable write data register of the RAM; a load data storage means that is loaded at the same time as the initial microprogram load and stores a copy of the load data of the RAM; and when an error is detected in the read data register. The error address held in the address register is extracted, the data corresponding to the error address is read out from the load data storage means, and the data is stored in the RAM using the write data register.
1. A data processing device comprising: a failure processing device that rewrites data read from the computer. 2. The error address which is the content of the address register when an error is detected in the read data register, the error data which is the content of the read data register, and the content of the load data storage means corresponding to the error address. Claim 1 characterized by comprising: a fault information storage means for storing and storing fault information; and a means for pointing out a fault location based on the content of said fault information.
The data processing device described.