JPH0488634A - Method of forming thin film wiring - Google Patents

Abstract

PURPOSE:To avoid the defective step coverage on a metallic film by a method wherein the formation frequency of insulating film on the surface of the thin film wirings comprising metallic layer is restricted to the required minimim i.e., one coating of an upper layer insulating film. CONSTITUTION:The surface of a substrate 10 is coated with an under-neath insulating film 11. Next, the unnecessary parts of the film is removed by isotropical dryetching process simultaneously forming the stepped parts of the film 11 into the taper parts 12. Later, the surface on the film 11 side is coated with a metal to form a metallic film 13. Next, the metallic film 13 is coated with a resist 14. In this case, the surface of the resist 14 is formed into a flattened surface. Next, the resist 14 and the film 13 are etched away to remove the part from the surface of the resist 14 to the surface of the film 12 in even thickness. Through these procedures, the thin film wirings 15 comprising the film 13 are formed in the substrate 10 while the surface of the wirings 15 and the film 11 can be flattened. Later, an upper layer insulating film 16 is formed on the surfaces of the wirings 15 and the film 11 to be formed into one body therewith 15, 11. In this case, the film 16 is formed only one time especially on the surfaces of the wirngs 15 thereby enabling the hillock formation to be restrained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method for forming thin film wiring in multilayer wiring of semiconductor devices M and the like.

[Prior Art J] In recent years, in semiconductor devices, there has been a demand for multi-layer wiring as the integration becomes higher, the density becomes higher, and the operation speed becomes faster. Multilayering of wiring can substantially reduce the wiring area to prevent the chip from becoming larger, and shorten the average wiring length to suppress delays in operating speed due to wiring resistance. Among the manufacturing processes for realizing a semiconductor device with such a multilayer wiring structure, the process of flattening the wiring is particularly important. That is, if an uneven portion exists in the interlayer insulating film due to the wiring pattern in the lower layer, defective step coverage will occur when forming the wiring film in the upper layer, resulting in defective disconnection of the wiring. For this reason, flattening the surface of the interlayer insulating film is important in realizing highly reliable multilayer wiring.

As this planarization method, an etch-back method as shown in FIG. 2 is conventionally known. In this etch-back method, first, as shown in FIG. 2(A), a metal wiring 2 made of At or the like is patterned on a substrate l such as a semiconductor wafer, and then a base insulating film 3 is formed on the surface by the CVD method. Then, a resist 4 is applied to the surface of the base insulation film 3 by a spin coating method or the like so that the surface becomes flat. And the second
As shown in Figure (B), the resist 4 and the base insulating film 3 are etched under non-selective conditions to remove a uniform thickness from the surface of the resist 4 to the surface of the metal wiring 2. As a result, the surface of the base insulation #3 remaining on the substrate 1 without being removed is flattened to the same plane as the surface of the metal wiring 2. Thereafter, as shown in FIG. 2(C), the upper layer insulating film 5 is again deposited on the surfaces of the base insulating film 3 and the metal wiring 2 by the CVD method. As a result, the surface of the upper layer insulating film 5 is covered with the lower layer base insulation [l! 3 and metal wiring 2 on a flat surface parallel to the surfaces thereof, this serves as an interlayer insulating film and enables multilayer wiring.

[The invention attempts to solve the problem.] ! [II] However, in the above-mentioned etch-back method, two insulating lI3.5 layers are deposited on the gold fi wiring 2 by the CVD method.
Protrusions called hillocks are likely to occur on the surface of the metal wiring 2, and these hillocks cause the upper layer insulating layer, which is an interlayer insulating film, to
There is a problem in that a defect occurs in 15, causing a short circuit between the multilayer wiring, and reducing the reliability of the wiring. Moreover, in the above-mentioned etch-back method, since the metal wiring 2 is patterned in advance on the substrate l, uneven parts are formed due to the metal wiring 2, and when forming the base insulating film 3 on the surface, step and puckerage defects occur. is more likely to occur. Therefore, there is a constraint that the base insulating film 3 must have a property that does not easily cause step coverage defects, that is, a property that easily adheres to the steps of uneven portions.

An object of the present invention is to provide a method for forming thin film wiring that suppresses the occurrence of hillocks, enables highly reliable multilayer wiring, and does not cause stepping force failures.

[Means for Solving the Problems] In order to achieve the above-mentioned objects, the present invention deposits a base insulating film on a substrate, and butterens the base insulating film by isotropic etching to form a base insulating film. In addition to removing unnecessary parts of the film, steps of the underlying insulating film are formed on the tapered portions, a metal film is grown on these surfaces, and a temporary insulating film is applied on this metal film. Then, the metal film is removed by etching from the surface of the temporary insulating film to the surface of the base insulating film to form a thin film wiring made of the metal film, and the upper insulating layer is formed on the thin film wiring and the surface of the base insulating film. It is to form a film.

[Function] According to the present invention, the number of times an insulating film is formed on the surface of a thin film wiring made of a metal layer is reduced to the necessary minimum, that is, the upper layer insulating film is formed once.
It is possible to suppress the generation of hillocks on the surface of the thin film wiring by suppressing the occurrence of hillocks on the surface of the thin film wiring, and by buttering the underlying insulating film by isotropic etching, the steps of the underlying insulating film can be removed. By forming a metal film and depositing a metal film on this tapered portion, it is possible to prevent step coverage defects of the metal film.

[Embodiment] Hereinafter, an embodiment of the present invention will be described with reference to FIGS. 1(A) to 1(F).

First, as shown in FIG. 1(A), a base insulating film 11 is deposited on the surface of a substrate 10 by the CVD method. In this case, the substrate 10 is a silicon wafer, ceramic, glass, quartz, or the like. Further, as the base insulating film 11, 5iO
z, SiN, etc., and there is no unevenness on the surface of the substrate IO, so there is no need to use a material with particularly good step coverage.

Next, as shown in FIG. 1B, unnecessary portions of the base insulating film 11 are removed by isotropic dry etching, and steps of the base insulating film 11 are formed on the taber fi 12 by isotropic dry etching. Etching uses CF as a reactive gas.
i. This is plasma etching using CFs-02 or the like, and steps in the base insulating film 11 are formed in a tapered shape. When performing isotropic dry etching, a photoresist is patterned in advance on the base insulating film 11 by photolithography technology, and etching is performed using this photoresist as a mask.

Thereafter, as shown in FIG. 1C, a metal such as AI is deposited on the surface of the base insulating film 11 by vacuum evaporation or sputtering to form a metal film 13. At this time, a step in the base insulating film 11 is formed on the tape portion 12, and this tapered portion 1
Since the metal 1113 is deposited on the substrate 2, step coverage failure does not occur, and the metal film 13 can be formed with a uniform thickness along the surface of the base insulation @Ill.

Then, as shown in FIG. 1(D), a resist (temporary insulating film) 14 is coated on the metal film 13 by a spin code method. In this case, even if the surface of the metal film 13 is formed in an uneven shape, the surface of the resist 14 is formed in a flat surface.

Next, as shown in FIG. 1E, the resist 14 and metal M13 are etched under non-selective conditions to remove a uniform thickness from the surface of the resist 14 to the surface of the base insulating film 11. This etching is etching that is not selective to the materials of the resist 14 and metal film 13,
Can be wet etched or dry etched.
As a result, unnecessary metal film 13 and resist 14 on base insulating film ll are removed, thin film wiring 15 made of metal film 13 is formed on substrate 10, and thin film wiring 1
5 and the surfaces of the base insulating film 11 are planarized.

Thereafter, as shown in FIG. 1F, an upper layer insulating film 16 is again formed on the surfaces of the thin film wiring 15 and the base insulating film 11 by the CVD method, and is integrated with the base insulating film 11. At this time, since the surfaces of the base insulating film 11 and the thin film wiring 15 are planarized, the surface of the upper layer insulating film 16 is also formed flat, and the upper layer thin film wiring can be formed satisfactorily on this surface. In this case, especially since the upper layer insulation mis is formed only once on the surface of the thin film wiring 15, the occurrence of hillocks can be suppressed. Therefore, the hillock can prevent defects occurring in the upper layer insulation 1116 and short circuits between the thin film wiring formed on the upper layer and the lower layer thin film wiring 15, and it is possible to manufacture multilayer wiring with high upward slope. becomes.

[Effects of the Invention] As explained in detail above, according to the present invention, the number of times an insulating film is formed on the surface of a thin film wiring can be minimized, and
It is possible to suppress the occurrence of hillocks on the surface of thin film wiring, thereby preventing defects in the upper layer insulating film and short circuits between multilayer wiring, making it possible to realize multilayer wiring with high conductivity. Moreover, by depositing the base insulating film on the surface of the substrate, the base insulating film is not limited by the material.
The selection range of materials can be expanded, and the base insulating film is patterned by isotropic etching to form a step in the base insulating film on the tapered part, and the metal film is coated on this tapered part. does not cause step coverage failure,
A metal film can be formed to have a uniform thickness.

[Brief explanation of the drawing]

FIGS. 1(A) to (F) are cross-sectional views showing the process of forming a thin film wiring according to the present invention, and FIGS. 2(A) to (C) are cross-sectional views showing the process of forming a conventional thin film wiring. . 10...Substrate, 11...Base insulating film,
12...Taber part, 13...Metal film,
14...Resist (temporary insulating film), 15...
...Thin film wiring, 16... Upper layer insulating film.

Claims (1)

[Claims] A base insulating film is deposited on a substrate, and this base insulating film is patterned by isotropic etching to remove unnecessary portions of the base insulating film and to form a step in the base insulating film at a tapered portion. , a metal film is grown on these surfaces, a temporary insulating film is applied on this metal film, and the temporary insulating film and the metal film are etched to form a uniform thickness of the base layer from the surface of the temporary insulating film. 1. A method for forming a thin film wiring, comprising forming a thin film wiring made of the metal film by removing up to the surface of the insulating film, and forming an upper insulating film on the surface of the thin film wiring and the base insulating film.