JPH0488638A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce a heat treatment for diffusion and to make possible the formation of an emitter region of a junction, which contains a high-concentration impurity and is shallow, by a method wherein an impurity diffusion method, in which an impurity is diffused from a polycrystalline silicon film having high- concentration impurity-containing sidewalls or from an oxide film, is used for the formation of the emitter region. CONSTITUTION:An impurity of a prescribed concentration is implanted and a polysilicon film having reduced resistance is patterned and is etched, whereby an emitter polysilicon region 13 is formed. After that, an N-type impurity is diffused from an N-type impurity diffusion source region 12, whose sidewall parts contain a high-concentration impurity, by performing a heat treatment, made to pass through the region 13 and an N<+> emitter region 14 is formed in the surface layer of an active base region 11b. Accordingly, as the high- concentration impurity is easily diffused in the surface of the region 11b from the region 12a in a high-concentration impurity diffusion process for forming the region 14, a high-concentration and shadow emitter junction can be formed also in the thin active base region 11b with good controllability and good reproducibility.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a bipolar semiconductor device.
Depositing a layer of polysilicon, forming the paste, collector isolation and base, emitter in a self-aligned manner,
The present invention relates to a method for manufacturing a two-layer polysilicon self-aligned bipolar transistor (hereinafter referred to as DPsA transistor) in which a polysilicon resistor is also formed at the same time.

[Conventional technology]

FIG. 4 shows a conventional method of manufacturing a DPSA transistor disclosed in Japanese Patent Application Laid-Open No. 63-261746.

In the figure, 2 is an n-type buried diffusion layer, 3 is an n epitaxial growth layer, 4 is a trench isolation buried oxide film, 6a is a base electrode polycrystalline silicon, 828 is a base and emitter isolation oxide film, 9 is a nitride film, and 11a is a external base area, l
lb is the active base region, 13 is polysilicon, and 14 is n.
° Emitter region, 15b is emitter silicide bridge, 1
9 is platinum silicide 1, 20, 30 is an oxide film, and 22 is non-doped polysilicon.

The manufacturing method will be explained below.

First, an oxidation-resistant film 9 such as a first polysilicon, a thin oxide M30, and a nitride film is sequentially deposited on the element formation region separated by the insulating oxide film 4. And the oxidation resistance Ws
9 is removed and the first polysilicon region exposed on the surface is oxidized.

Next, a second conductivity type impurity is doped through the unoxidized first polysilicon region 6a, and the first region 1
1a (external base region), the oxidized first
The polysilicon region is removed to expose the surface of the element formation region, and a thin oxide film 28 is provided on the exposed portion (fourth
Figure (a)).

Next, after forming a second region 11b (active base region) of the second conductivity type, a CVD oxide film 8 and a second polysilicon 22 are sequentially deposited (FIG. 4(b)).

Further, the second polysilicon 22 and the CVD oxide film 8 are anisotropically etched, and the second polysilicon 22 and the CVD oxide film 8 are etched only on the sidewalls of the region where the oxidized first polycrystalline silicon is removed.
The VD oxide film 8 is left and the surface of the second region 11b of the second conductivity type is exposed (FIG. 4(C)).

Next, third polysilicon 11!113 is deposited on the entire surface, and the surface is silicided to form a silicide layer 15b (FIG. 4(d)).

Then, impurities of the first conductivity type are implanted into the third polysilicon film 13, and the impurities of the first conductivity type are diffused from the surface of the third polysilicon film 13 to form the first conductivity type impurities on the surface of the second region 11b.
Conductivity type impurity diffusion region 12 (forms an emitter region, emitter region 12 or external base region ILa)
, a third polysilicon fill other than the region including the active base region 11b; 3. Silicide Ill 5 b
, the nitride film 9 is removed (FIG. 4(e)).

Thereafter, a platinum silicide film 19 is formed on the exposed surface of the first polysilicon film 6a, and then an oxide film 20 is formed on the entire surface to obtain the structure shown in FIG.

As another manufacturing method, after the step shown in FIG. 4C, the surface of the second region 11b of the second conductivity type is roughened through the opening of the first polycrystalline silicon film 6a. There is also a method of forming an n emitter region by introducing type impurities by ion implantation or the like, and then using the steps shown in FIG.

Furthermore, in such a conventional manufacturing method, the third polysilicon film 13 is formed on the entire surface in the step shown in FIG. A first conductivity type impurity is ion-implanted at a desired concentration from the surface region of the third polysilicon film 13 selected to form the emitter region 14, and also to form elements of the third polysilicon film 13. In areas other than the area, the desired concentration of f'f! is selectively applied. , a polysilicon resistor (not shown) can be formed by ion implantation.

The two-layer polysilicon self-aligned transistor manufactured by the above manufacturing method has a collector,
The base and emitter regions are determined in a self-aligned manner, and the emitter diffusion region 14 is formed using the upper third polysilicon 13. Then, wiring and polysilicon resistors are formed.

[Problem to be solved by the invention]

However, in the conventional manufacturing method, the third polysilicon I! I! 13, and the introduced first conductivity type impurity is diffused from the second polysilicon film 13 to the second conductivity type active base region 11b to form the emitter region 14. However, since this is diffusion from the surface, and shallow junction formation is also required for impurity diffusion, heat treatment at high temperatures and for long periods of time is not possible, making it impossible to form an emitter layer with sufficient concentration. be.

Further, even if the emitter layer 14 is formed in the active base layer 11b by ion implantation before forming the third polysilicon film 13, this is disadvantageous for forming a shallow junction.

This invention was made in order to solve the above-mentioned problems in the manufacturing method of two-layer polysilicon self-aligned transistors, and it is possible to form a highly doped emitter diffusion region and to form it with a shallow junction. The purpose of the present invention is to provide a method for manufacturing a semiconductor device.

[Means for Solving the Problems] A method for manufacturing a semiconductor device according to the present invention includes providing a first polycrystalline silicon film on the surface of an element formation region made of a semiconductor layer of a first conductivity type, selectively oxidizing the film, The first unoxidized
The polycrystalline silicon film of the first conductivity type and the second conductivity type are
Diffusing impurities of the conductivity type to form a first region of the first conductivity type and a second region of the second conductivity type, and removing the first polycrystalline silicon oxide film to form an opening. , a third region of the second conductivity type is formed in the element formation region exposed in the opening by implanting a second conductivity type impurity through a thin oxide film, and a highly concentrated impurity is implanted on the side wall of the opening. After forming a second polycrystalline silicon or oxide film containing impurities of one conductivity type and further depositing a third polycrystalline silicon, the first
A fourth region having a shallow junction with a sufficient impurity concentration is formed in the surface layer of the third region by impurity diffusion using the second polycrystalline silicon or oxide film containing conductivity type impurities as a diffusion source. It is something to do.

[Effect]

In the method for manufacturing a semiconductor device according to the present invention, an impurity diffusion method from the second polycrystalline silicon or oxide film containing high concentration impurities on the sidewall is used to form the fourth region, that is, the emitter region. Compared to the method of diffusing from the polysilicon surface, high-concentration impurities are diffused from a region close to the substrate, reducing heat treatment for diffusion, and forming a shallow junction emitter region with high-concentration impurities.

〔Example] An embodiment of the present invention will be described below with reference to the drawings.

FIGS. 1(a) to (e) are cross-sectional views of each main process showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. In particular, in this embodiment, a method for manufacturing a bipolar semiconductor device is taken as an example. I am using it.

In the figure, 1 is a p-type substrate, 2 is an n'' buried diffusion layer, 3 is an n'' epitaxial growth layer, 4 is a trench isolation buried oxide film, 5 is an oxide film, 6a is a base electrode polycrystalline silicon,
6b is collector bridge polycrystalline silicon, 7 is base, collector isolation oxide film, 8 is base, emitter isolation oxide film, 8
b is a thin oxide film, 9 is a nitride film, 10 is an n'' collector all region, lla is an external base region, llb is an active base region, 12 is n-type polycrystalline silicon containing high concentration impurities,
12a is an emitter impurity diffusion source region, 13 is polycrystalline silicon, 14 is an n-emitter region 15a is a base silicide electrode, 15b is an emitter silicide electrode, and 15c is a collector silicide electrode.

Next, the manufacturing method of this example will be explained.

First, an n-type impurity is diffused into a p-type substrate 1 to form an n-buried collector layer 2, and then a low concentration n-type growth layer 3 is formed thereon by epitaxial growth or the like. In the semiconductor layer thus formed, an element formation region is isolated by a buried oxide film region 4 for trench isolation and a surface field oxide film 5.

After that, a first polysilicon film is provided on the entire surface, and an oxidation-resistant film 9 such as a nitride film is deposited on it through a thin oxide WA 8 to form a separation region between an external base region and a collector lead-out region, and an active base region. The oxidation-resistant film 9 is patterned and removed at locations corresponding to .

Thereafter, after selectively oxidizing the exposed first polysilicon using the remaining oxidation-resistant film 9 as a mask, n
A type impurity and a p-type impurity are introduced to form a collector all region 10 (first region) and an external base region (second region) 11a.

Thereafter, after removing the polysilicon oxide film on the active base region, a thin oxide film 1!18b is formed on the removed portion, and p-type impurities are introduced through this by ion implantation, etc., and the active base region 11b ( the third region) and the first
The structure shown in Figure (a) is obtained.

Next, a second polysilicon 12 containing a high concentration of n-type impurities is formed.
is deposited on the entire surface (Fig. 1(b)).

Then, the deposited second polysilicon 12 is anisotropically etched to open an emitter region, and at the same time leave it on the side wall of the opening and emitter impurity diffusion rA region 12.
a (Fig. 1(C)).

Next, after depositing third polysilicon over the entire surface, a patterned resist mask is used to form the active base region 11.
A first conductivity type impurity is ion-implanted at a desired concentration into the selected third polysilicon containing polycrystalline silicon from the surface region, thereby lowering the resistance of the third polysilicon.

Thereafter, the emitter polysilicon region 13 is etched by buttering and etching the third polysilicon.
(Fig. 1 (d3)).

After that, by performing heat treatment, the n-type impurity is diffused from the high concentration n-type impurity diffusion region 12a of the side wall portion,
An n' emitter region 14 is formed in the surface layer of the active base region 11b through the emitter polysilicon region 13.

Then, silicide films are formed on the surfaces of the first and third polysilicon rows a and 13, respectively, and these are used as a base silicide electrode 15a, an emitter silicide electrode 15b, and a collector silicide electrode 15c, forming the structure shown in FIG. 1(e). obtain.

Note that in the above embodiment, the emitter impurity diffusion source region 12a
Although the second polysilicon film is made of the second polysilicon containing a high concentration of n-type impurity, it may be a CVD oxide film containing a high concentration of n-type impurity.

Next, the details of the process of forming the emitter region 14 of this example are shown in FIG.

As shown in the figure, an emitter impurity diffusion source region 12a made of polysilicon containing a high concentration of n-type impurity or a CVD oxide film containing a high concentration of n-type impurity is connected to an active base layer 11b.
The first polysilicon tllF6a is very close to the surface of
is formed on the side wall of the opening. Therefore, in the high concentration impurity diffusion step for forming the emitter region I4, the high concentration impurity is easily diffused from the region 12a to the surface of the active base region Ilb, so that the high concentration impurity is also diffused into the thin active base region 11b. Furthermore, shallow emitter junctions can be formed with good controllability and reproducibility.

Therefore, in this embodiment, the base and collector are separated,
In addition, the base region and emitter region can be formed in a self-aligned manner, and the emitter region 14 can be formed thinly and with high concentration, so the contact resistance of the emitter region 14 can be reduced to a small value, making it possible to form a high-speed, high-performance pibor transistor. Manufacturing becomes possible. Furthermore, it is possible to improve carrier injection efficiency, allowing a large amount of current to flow between the emitter and the collector, and reducing power consumption.

Next, a case will be described in which a polysilicon resistor is simultaneously manufactured using the manufacturing method of the above embodiment.

As shown in FIG. 3(a), after the step of FIG. 1(C) above, a third polysilicon is deposited on the entire surface in the same way as the step of FIG. 1(d), and the active base region 11b is At the same time, impurities of a desired concentration are selectively implanted into regions other than the element formation region of the third polysilicon to form a polysilicon resistor. After that, the emitter polysilicon region 13. is formed by patterning and etching.
and a polysilicon resistor 131.

Thereafter, as shown in FIG. 3(b), the emitter region 14 is formed by impurity diffusion from the sidewall by the method described above, and then the surfaces of the first and third polysilicon rows a and 13 and the polysilicon Contact a on the surface of resistor 131
Silicide electrodes 15a and 15c are formed in each region.

According to such a method, the polysilicon resistor 1 can be formed at the same time without increasing the number of steps in the method of the above embodiment.
31 can also be formed.

Furthermore, although the above embodiment describes a two-layer polysilicon self-aligned bipolar transistor, this embodiment is not limited to this structure, and is applicable to the manufacture of all bipolar semiconductor devices having shallow junctions. It is possible.

[Effects of the Invention] As described above, according to the present invention, after the first polycrystalline silicon film is selectively oxidized, the polycrystalline silicon oxide film formed by the selective oxidation is removed to form an opening, and the first polycrystalline silicon film is selectively oxidized. Polysilicon containing high concentration impurities or CVD oxide film containing high concentration impurities is provided on the side wall of the opening as an emitter impurity diffusion flTJ region, and after forming the emitter polysilicon to cover the opening, the emitter on the side wall is・Since the emitter region is formed by diffusing high concentration impurities from the ivy impurity diffusion source region, unlike diffusion from the surface layer of emitter polysilicon, it is possible to form a highly concentrated and shallow emitter junction. An emitter region can be precisely formed on the surface of a thin active base layer, which has the effect of making it possible to manufacture high-speed high-voltage transistors. Furthermore, this has the effect of lowering the resistance of the emitter polysilicon and reducing the contact resistance.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a method for manufacturing a bipolar semiconductor device according to an embodiment of the present invention, and FIG. 2 is a diagram showing details of an emitter forming step in a method for manufacturing a bipolar semiconductor device according to an embodiment of the present invention. 3 are diagrams showing part of the steps of a method for manufacturing a bipolar semiconductor device according to another embodiment of the present invention, and FIG. 4 is a diagram showing a conventional method for manufacturing a bipolar semiconductor device. In the figure, 1 is a p-type substrate, 2 is an n-buried diffusion layer, 3 is an n-epitaxial growth layer, 4 is a trench isolation buried oxide film, 5 and 5a are oxide films, 6a is a base electrode polycrystalline silicon, and 6b is a Collector electrode polycrystalline silicon, 7 is base, collector isolation oxide film, 8 is base, emitter isolation oxide film, 8b is oxide film, 9 is nitride film, 10 is n゛collector all region lla is external base region, llb is active Base region, 12 is n-type polysilicon containing high concentration impurity, 1
2a is the emitter impurity expansion area, 13 is polysilicon, 14 is the n emitter battle area 15a is the base silicide electrode, 15b is the emitter silicide Xpi, 15c is the collector silicide electrode, 15d is the silicide electrode, 131
is a polysilicon resistor. In addition, in the figures, the same reference numerals indicate the same or corresponding parts. Figure 1

Claims (1)

[Claims] (1) Depositing a first polycrystalline silicon film on an island-shaped element formation region made of a semiconductor layer of a first conductivity type, and selectively oxidizing the same; and the first polycrystalline silicon film. diffusing impurities of the first conductivity type and the second conductivity type using the mask as a mask to form a first region of the first conductivity type and a second region of the second conductivity type in the element formation region, respectively; The polycrystalline silicon oxide film of No. 1 is removed to form an opening, and a second conductivity type impurity is implanted through the thin oxide film to form a second conductivity in the element forming region exposed in the opening. a step of forming a third region of the mold; and a step of forming a second polycrystalline silicon or oxide film containing a high concentration of impurities of the first conductivity type on the sidewall of the opening; a step of introducing a first conductivity type impurity into a region including the third region; using the second polycrystalline silicon or oxide film on the side wall of the opening as a diffusion source; manufacturing a semiconductor device, comprising the step of: diffusing a first conductivity type impurity into the third region through the third polycrystalline silicon to form a fourth region of the first conductivity type; Method.