JPH0488647A - Inspection substrate and method and device for circuit board inspecting - Google Patents
Inspection substrate and method and device for circuit board inspectingInfo
- Publication number
- JPH0488647A JPH0488647A JP2203271A JP20327190A JPH0488647A JP H0488647 A JPH0488647 A JP H0488647A JP 2203271 A JP2203271 A JP 2203271A JP 20327190 A JP20327190 A JP 20327190A JP H0488647 A JPH0488647 A JP H0488647A
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- probe
- terminals
- inspection
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Supply And Installment Of Electrical Components (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は半導体ウェファ−や多層I&板等の回路基板を
検査する方法、検査基板並びに回路基板検査装置に関係
する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for testing circuit boards such as semiconductor wafers and multilayer I&boards, to testing boards, and to circuit board testing apparatus.
従来の技術
従来の回路基板の検査方法は、複数個の接触針(プロー
ブ)を−枚の板上に並べたもの(プローブカード)を被
検査回路基板に押し当て、プローブを被測定ランド(被
検査回路基板上のパターン状の導体、ランド等)に接触
させ、このプローブに信号を送ったりあるいは受けたり
して、被検査回路基板が正常にできているかどうかを検
査した。2. Description of the Related Art In the conventional circuit board testing method, a plurality of contact needles (probes) arranged on a board (probe card) are pressed against the circuit board to be tested, and the probes are placed on the land to be measured (tested land). The probe was brought into contact with patterned conductors, lands, etc. on the test circuit board, and signals were sent to and received from the probe to test whether the circuit board to be tested was properly formed.
発明が解決しようとする課題
ところが、最近は機器の小型化が進み止どまるところを
知らない。小型化のために、極魔に高密度の実装が行わ
れ、−枚の基板上に1000を超すランドも珍しくなく
なっている。かつ、ランド間のピンチも詰まってきてお
り、プローブを立てて検査することが不可能にさえなっ
てきた。半導体ウェファ−の場合は現在部分的にプロー
ブを立てているに過ぎない。Problems that inventions aim to solve However, recently, the miniaturization of devices has continued and there is no stopping point. In order to achieve miniaturization, extremely high-density packaging is being carried out, and it is not uncommon for there to be over 1,000 lands on a single board. In addition, the gaps between the lands have become clogged, making it even impossible to stand the probe up for inspection. In the case of semiconductor wafers, probes are only partially erected at present.
lIBを解決するための手段
本発明はこのような課題を解決するために、出力端子に
電圧を印加したり、接地したりできる複数個の電圧印加
接地回路を保有し、その出力端子をプローブ端子とする
半導体ウェファ−からなる検査基板があり、このプロー
ブ端子を被検査回路基板上の被測定ランドに押圧接触さ
せ、それぞれの電圧印加接地回路を働かせて指定のプロ
ーブ端子に電圧を印加し、他のプローブ端子を順次接地
して行き、流れるtiJtを測定して、被検査回路基板
を検査するようにしている。Means for Solving IIB In order to solve such problems, the present invention has a plurality of voltage application grounding circuits that can apply voltage to the output terminal and ground the output terminal, and connect the output terminal to the probe terminal. There is a test board made of a semiconductor wafer, and the probe terminals are pressed into contact with the lands to be measured on the circuit board to be tested, and each voltage application grounding circuit is activated to apply a voltage to the designated probe terminals. The circuit board to be tested is tested by sequentially grounding the probe terminals and measuring the flowing tiJt.
作用
本発明を用いれば、半導体ウェファ−上の端子(パッド
やバンプ)をプローブとしているために高密度の回路基
板であっても、また、被測定ランドが多くても簡単に検
査できる。Function Using the present invention, since terminals (pads and bumps) on a semiconductor wafer are used as probes, even if the circuit board has a high density or there are many lands to be measured, it can be easily inspected.
実施例
以下、本発明の回路基板検査方法、検査基板回路基板検
査装置の一実施例について図面を参照しながら説明する
。Embodiment Hereinafter, an embodiment of the circuit board inspection method and inspection circuit board inspection apparatus of the present invention will be described with reference to the drawings.
第1図は本発明の回路基板検査方法の原理説明図である
。FIG. 1 is an explanatory diagram of the principle of the circuit board inspection method of the present invention.
被検査回路基板101上の被測定ランド(ランド等外装
配線)106は内装配線105により同一表面あるいは
他の面上の他の被測定ランド(ランド等外装配線)に接
続されている。この被検査回路基板の配線状態が望むも
のに出来上がりでいるかどうかを検査する。検査基板1
02はシリコンやガリウム砒素等の半導体ウェファ−で
あり、第1図では簡略化して措いである。プローブ端子
103は被検査回路基板の被測定ランドと同し位置に配
置してあり、圧接することにより、被測定ランドを接触
する。接触のよいプローブ端子には金バンプ等導電性が
良く突起のあるものを形成するのが良い。各プローブ端
子は、半導体ウェファ−上に作った複数個の電圧印加接
地回路104の出力端子である。各電圧印加接地回路は
接地端子107に入る検査信号(検査するための信号)
により動作する。接続端子107は、また外部に送る検
査信号(被検査回路基板から得られる情報)や電源等の
ための接続端子でもある。108は検査信号発生装置1
09と検査基板103を結ぶケーブルである。検査信号
発生装置109は予め設定したプログラムで電圧印加接
地回路を働かせ、それによって得られる被検査回路基板
からの情報を処理し、被検査回路基板の検査を行う。Lands to be measured (exterior wiring such as lands) 106 on the circuit board to be inspected 101 are connected by internal wiring 105 to other lands to be measured (exterior wiring such as lands) on the same surface or another surface. It is inspected whether the wiring condition of the circuit board to be inspected is as desired. Inspection board 1
02 is a semiconductor wafer made of silicon, gallium arsenide, etc., which is simplified in FIG. The probe terminal 103 is arranged at the same position as the land to be measured on the circuit board to be tested, and contacts the land to be measured by pressing the probe terminal 103 into contact with the land to be measured. It is preferable to form a probe terminal with good conductivity and protrusions, such as a gold bump, as a probe terminal with good contact. Each probe terminal is an output terminal of a plurality of voltage applying ground circuits 104 formed on a semiconductor wafer. Each voltage application ground circuit receives a test signal (signal for testing) that enters the ground terminal 107.
It works by The connection terminal 107 is also a connection terminal for a test signal (information obtained from the circuit board to be tested) sent to the outside, a power supply, and the like. 108 is a test signal generator 1
09 and the test board 103. The test signal generator 109 operates the voltage application grounding circuit according to a preset program, processes information obtained from the circuit board to be tested thereby, and tests the circuit board to be tested.
被検査回路基板101を2枚の検査基板103で挟み、
位置をあわせて圧接して(圧接機構は措いていない)、
被検査回路基板上の各被測定ランドと検査基板上の各プ
ローブ端子を各各接触させる。検査信号発生装置からの
指令で電圧印加接地回路により、検査基板の一つのプロ
ーブ端子に電圧を発生させ、一方、他のプローブ端子を
順次接地し、流れる電流を測定して行く。この湾定結果
は検査信号発生装置で予め設定された値と比較し、正常
か否かが判断される。すべてのプローブ端子について、
この検査を実行すれば、検査が完了する。A circuit board to be tested 101 is sandwiched between two test boards 103,
Align the positions and press them together (pressing mechanism is not included),
Each land to be measured on the circuit board to be tested is brought into contact with each probe terminal on the board to be tested. In response to a command from the test signal generator, a voltage application ground circuit generates a voltage at one probe terminal of the test board, while the other probe terminals are grounded one after another, and the flowing current is measured. This determination result is compared with a value set in advance by the test signal generator to determine whether it is normal or not. For all probe terminals,
Executing this test completes the test.
導通あるいは抵抗値検査は望むプローブ端子間に望む電
流が流れるかどうかを検査すればよい。Continuity or resistance value testing can be performed by checking whether a desired current flows between desired probe terminals.
また、リーク検査は望むプローブ端子以外のプローブ端
子に流れる電流を検査すればよい。Furthermore, the leakage test may be performed by testing the current flowing through probe terminals other than the desired probe terminal.
被検査回路基板上の被測定ランドと検査基板上のプロー
ブ端子の接触は難しい。被測定プローブ端子の数が多く
なればなるほど難しい。接触を良くするために、異方導
電性のWs(液晶表示パネルの端子引き出しに良く使わ
れる)を検査基板のプローブ端子表面につけると良い。It is difficult to make contact between the land to be measured on the circuit board to be tested and the probe terminal on the board to be tested. The greater the number of probe terminals to be measured, the more difficult it becomes. In order to improve the contact, it is recommended to attach anisotropically conductive Ws (often used for drawing out terminals of liquid crystal display panels) to the surface of the probe terminals of the test board.
また、位置をあわせ押圧するための圧接機構は必要であ
る。In addition, a pressure contact mechanism for positioning and pressing is required.
被検査回路基板が半導体ウェファ−のように被測定ラン
ドが基板の一方の面にしかない場合でも、何等変わると
ころがない。検査基板が1枚で済むだけである。Even if the circuit board to be tested is a semiconductor wafer, where the land to be measured is only on one side of the board, there is no difference. Only one board is required for inspection.
第2図は本発明の検査方法をより具体的に説明する具体
例である。FIG. 2 is a specific example for more specifically explaining the inspection method of the present invention.
被検査回路基板202の被測定ランドに検査基板のプロ
ーブ端子を接触させ、電圧印加接地回路201の各出カ
ブローブ端子Bを図のように接触する。The probe terminal of the test board is brought into contact with the land to be measured on the circuit board to be tested 202, and each output probe terminal B of the voltage application grounding circuit 201 is brought into contact as shown in the figure.
電圧印加接地回路201は2つのトランジスタからでき
ていて、信号端子Sへの信号に従って端子Aから出力端
子Bに電流を流し出す、また、信号端子りへの信号によ
り出力端子Bを接地する。The voltage application grounding circuit 201 is made up of two transistors, and causes current to flow from terminal A to output terminal B in accordance with a signal to signal terminal S, and also grounds output terminal B in accordance with a signal to signal terminal S.
この図では方法を説明するために省略して描いていて、
信号端子AやDへの信号電圧レベルなど詳細については
考慮していない、単に概念を表しているに過ぎない。This figure is omitted to explain the method.
Details such as signal voltage levels to signal terminals A and D are not considered, and the concept is merely expressed.
206は検査信号発生装置の一部を示したもので、20
3は電流値測定用の抵抗である。一端は電源に、他の一
端は全て電圧印加接地回路の端子Aに接続しである。2
04はデコーダで接地端子指定コード207により、指
定の電圧印加接地回路に接地信号を送り、指定された出
力端子Bを接地する。206 shows a part of the test signal generating device;
3 is a resistor for measuring current value. One end is connected to the power supply, and the other ends are all connected to terminal A of the voltage application grounding circuit. 2
04 is a decoder which sends a grounding signal to a designated voltage application grounding circuit using a grounding terminal designation code 207 to ground the designated output terminal B.
205もデコーダであり、印加端子指定コード208に
より、指定の電圧印加接地回路に印加信号を送り、指定
された出力端子Bを抵抗203を通して電源に接続する
。205 is also a decoder, which sends an application signal to a specified voltage application grounding circuit using an application terminal designation code 208, and connects a specified output terminal B to the power supply through a resistor 203.
検査方法の一例は、例えば、印加端子指定コード208
にて出力端子B1に電圧を発生させる。An example of the inspection method is, for example, the application terminal designation code 208
A voltage is generated at the output terminal B1.
次に、接地端子指定コード207により、出カブローブ
端子BOからB15まで順次接地して行く。Next, using the grounding terminal designation code 207, the output probe terminals BO to B15 are grounded in sequence.
図のような被検査回路基板の結線の場合は、出カブロー
ブ端子B1と83が接地されたときにのみ電流が流され
て、抵抗203に電圧降下があり、正常に結線できてい
ることを確認できる。もしそれ以外で電圧降下があれば
、ショートしているのであって、異常を発見できる。こ
のプロセスを全てのプローブ端子に行えば(BOから8
15まで順次電圧を印加して調べる)、被検査回路基板
が正常に作られているかどうかがわかる。In the case of the wiring of the circuit board under test as shown in the figure, current flows only when the output probe terminals B1 and 83 are grounded, and there is a voltage drop across the resistor 203, confirming that the wiring is properly connected. can. If there is a voltage drop at any other point, there is a short circuit, and you can discover the abnormality. If you do this process for all probe terminals (BO to 8
15), it can be seen whether the circuit board to be tested is manufactured normally.
この検査方法では単なる導通検査だけではなく、電圧降
下の大きさで抵抗値もはかれる。また、容量やインダク
タンスも計れる。また、プローブ端子間や浮遊容量やイ
ンダクタンス7 リークなども検査できる0図において
電圧印加接地回路が余っているが、検査には差し支えの
ないものである。This testing method not only tests for continuity, but also measures the resistance value based on the magnitude of the voltage drop. You can also measure capacitance and inductance. In addition, although there is an extra voltage application grounding circuit in Figure 0, which can inspect leakage between probe terminals, stray capacitance, and inductance, it does not pose any problem for inspection.
容易に考えられることであるが、原理、並びに具体例に
示したのは一例であって、回路構成、信号印加方法など
多くの変形がある0例えば、電圧印加接地回路でも、電
流を流し出す能力と吸い込む能力があれば機能を果たす
ことができる。すなわち、少々の抵抗があっても、後で
、計真して補償することもできる。また、検査基板上に
幾らかの信号処理回路を載せてしまい、検査信号発生装
置とのやりとりを簡単にしてしまうこともできる。Although it is easy to imagine, the principles and specific examples shown are just examples, and there are many variations in circuit configuration, signal application method, etc.For example, even in a voltage application grounded circuit, the ability to flow current If you have the ability to inhale, you can perform your functions. In other words, even if there is some resistance, it can be compensated for later. Furthermore, some signal processing circuits may be mounted on the test board, thereby simplifying communication with the test signal generator.
検査基板上のプローブ端子について、被検査回路基板上
の被測定ランドに対応した位置に設けであるとしたが、
一対一に対応している必要はない。Regarding the probe terminals on the test board, it was stated that they should be provided at positions corresponding to the lands to be measured on the circuit board to be tested.
There is no need for a one-on-one correspondence.
例えば、プローブ端子を被測定ランドの形状より細かく
格子状に配列することも可能である。また、被検査回路
基板の被測定ランドの位置に従って、半導体ウェファ−
上に一面に敷き詰めて作った電圧印加接地回路の内、対
応する位置にあるものにだけバンプを付けることも可能
である。この場合は、検査基板を被検査回路基板毎に作
る必要はない。For example, it is also possible to arrange the probe terminals in a grid pattern that is finer than the shape of the land to be measured. Also, according to the position of the land to be measured on the circuit board to be tested, the semiconductor wafer
It is also possible to attach bumps only to those at the corresponding positions among the voltage application grounding circuits that are laid out all over the top. In this case, it is not necessary to create a test board for each circuit board to be tested.
検査信号発生装置はパーソナルコンピュータのようなも
のであっても良いし、専用の物であっても良い。The test signal generating device may be something like a personal computer, or may be a dedicated device.
発明の効果
以上の説明から明らかなように、本発明を用いれば、従
来困難であった高密度大規模の回路基板を簡単に検査す
ることができ、回路基板の偉績性を挙げることができる
ばかりでなく、検査コストを大幅に下げることができる
。Effects of the Invention As is clear from the above explanation, by using the present invention, it is possible to easily inspect high-density, large-scale circuit boards, which was difficult in the past, and the great performance of circuit boards can be improved. However, inspection costs can be significantly reduced.
第1図は本発明の回路基板の検査方法の原理説明図、第
2図は本発明の回路基板の検査方法を具体的に説明する
構成動作説明図である。
101・・・・・・被検査回路基板、+02・曲・検査
基板、103・・・・・・プローブ端子、10.4・旧
・・電圧印加接地回路、105・・・・・・内装配線、
106・・・・・・被測定ランド、107・・・・・・
接続端子、108・・・・・・接続ケーブル、109.
206・・・・・検査信号発生装置、201・・・・・
・電圧印加接地回路、202・・・・・・被検査回路基
板、203・・・・・・抵抗、204・・・・・・接地
端子指定デコーダ、205・・・・・・電圧印加端子指
定デコーダ、207・・・・・・接地端子指定コード、
208・・・・・・電圧印加端子指定コード。FIG. 1 is a diagram illustrating the principle of the circuit board testing method of the present invention, and FIG. 2 is a diagram illustrating the configuration and operation specifically explaining the circuit board testing method of the present invention. 101...Circuit board to be tested, +02...Block/Test board, 103...Probe terminal, 10.4...Old voltage application grounding circuit, 105...Internal wiring ,
106...Land to be measured, 107...
Connection terminal, 108... Connection cable, 109.
206...Test signal generator, 201...
・Voltage application ground circuit, 202...Circuit board to be inspected, 203...Resistor, 204...Ground terminal designation decoder, 205...Voltage application terminal designation Decoder, 207... Ground terminal designation code,
208... Voltage application terminal designation code.
Claims (8)
複数個の電圧印加接地回路を保有し、その出力端子をプ
ローブ端子とする半導体ウエファーからなる検査基板が
あり、このプローブ端子を被検査回路基板上の被測定ラ
ンドに押圧接触させ、それぞれの電圧印加接地回路を働
かせて指定のプローブ端子に電圧を印加し、他のプロー
ブ端子を順次接地して行き、流れる電流を測定して、被
検査回路基板を検査する回路基板検査方法。(1) There is a test board made of a semiconductor wafer that has multiple voltage application grounding circuits that can apply voltage to output terminals and ground them, and uses the output terminals as probe terminals. Press it into contact with the land to be measured on the circuit board, apply voltage to the designated probe terminal by activating each voltage application grounding circuit, ground the other probe terminals in sequence, measure the flowing current, and A circuit board inspection method for inspecting an inspection circuit board.
2枚の検査基板のプローブ端子を接触させ、両検査基板
上の電圧印加接地回路を共に働かせて、被検査回路基板
を検査することを特徴とする請求項(1)記載の回路基
板検査方法。(2) Inspect the circuit board to be tested by bringing the probe terminals of the two test boards on both sides into contact with the lands to be measured on both sides of the circuit board to be tested, and activating the voltage application grounding circuits on both boards to be tested. The circuit board inspection method according to claim (1), characterized in that:
したりできる複数個の電圧印加接地回路を保有し、その
出力端子をプローブ端子とする半導体ウエファーからな
る検査基板。(3) A test board made of a semiconductor wafer, which has at least a plurality of voltage application grounding circuits capable of applying a voltage to or grounding an output terminal, and whose output terminals serve as probe terminals.
をプローブ端子とすることを特徴とする請求項(3)記
載の検査基板。(4) The test board according to claim (3), wherein a bump is provided on the output terminal of the voltage application grounding circuit and is used as a probe terminal.
覆い被検査回路基板の被測定ランドと検査基板のプロー
ブ端子とが接触しやすくしたことを特徴とする請求項(
3)から(4)のいずれかに記載の検査基板。(5) Claim (5) characterized in that the probe terminal surface of the test board is covered with an anisotropically conductive elastic body to facilitate contact between the land to be measured of the circuit board to be tested and the probe terminal of the test board.
The test board according to any one of 3) to (4).
したりできる複数個の電圧印加接地回路を保有し、その
出力端子をプローブ端子とする半導体ウエファーからな
る検査基板と、電圧印加接地回路を予め定められたよう
に動作させて接続関係を検査する検査信号発生装置と、
検査基板上のプローブ端子を被検査回路基板の被測定ラ
ンドに接触させる圧接機構とを有する回路基板検査装置
。(6) It has at least a plurality of voltage applying grounding circuits capable of applying voltage to the output terminals and grounding them, and includes a test board made of a semiconductor wafer whose output terminals are used as probe terminals, and a voltage applying grounding circuit. a test signal generator that operates in a predetermined manner to test connection relationships;
A circuit board testing device that includes a pressure contact mechanism that brings probe terminals on a test board into contact with lands to be measured on a circuit board to be tested.
を設けこれをプローブ端子としていることを特徴とする
請求項(6)記載の回路基板検査装置。(7) The circuit board inspection apparatus according to claim (6), wherein the inspection board has a bump provided on the output terminal of the voltage application grounding circuit and uses the bump as a probe terminal.
覆い被検査回路基板の被測定プローブ端子と検査基板の
プローブ端子とが接触しやすくしたことを特徴とする請
求項(6)から(7)のいずれかに記載の回路基板検査
装置。(8) From claim (6), characterized in that the probe terminal surface of the test board is covered with an anisotropically conductive elastic material to facilitate contact between the probe terminals of the circuit board to be tested and the probe terminals of the test board. The circuit board inspection device according to any one of (7).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2203271A JP2767991B2 (en) | 1990-07-31 | 1990-07-31 | Inspection board, circuit board inspection method and circuit board inspection apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2203271A JP2767991B2 (en) | 1990-07-31 | 1990-07-31 | Inspection board, circuit board inspection method and circuit board inspection apparatus |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0488647A true JPH0488647A (en) | 1992-03-23 |
| JP2767991B2 JP2767991B2 (en) | 1998-06-25 |
Family
ID=16471287
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2203271A Expired - Fee Related JP2767991B2 (en) | 1990-07-31 | 1990-07-31 | Inspection board, circuit board inspection method and circuit board inspection apparatus |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2767991B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011071450A (en) * | 2009-09-28 | 2011-04-07 | Murata Mfg Co Ltd | Method of manufacturing component built-in substrate |
-
1990
- 1990-07-31 JP JP2203271A patent/JP2767991B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011071450A (en) * | 2009-09-28 | 2011-04-07 | Murata Mfg Co Ltd | Method of manufacturing component built-in substrate |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2767991B2 (en) | 1998-06-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5198756A (en) | Test fixture wiring integrity verification device | |
| US3777260A (en) | Grid for making electrical contact | |
| US5969530A (en) | Circuit board inspection apparatus and method employing a rapidly changing electrical parameter signal | |
| US20080048689A1 (en) | Wafer type probe card, method for fabricating the same, and semiconductor test apparatus having the same | |
| US5263240A (en) | Method of manufacturing printed wiring boards for motors | |
| JPH0488647A (en) | Inspection substrate and method and device for circuit board inspecting | |
| CN100507578C (en) | Method for manufacturing wafer-level test circuit board and structure thereof | |
| JP2705288B2 (en) | Circuit board inspection method, inspection board, and circuit board inspection device | |
| JPS62269075A (en) | Apparatus for inspecting printed circuit board | |
| US20040032271A1 (en) | Anisotropic probing contactor | |
| JP3391302B2 (en) | Semiconductor test equipment | |
| US20080061812A1 (en) | Component-attach test vehicle | |
| JPH01318245A (en) | Probe card inspection jig | |
| JP3076424B2 (en) | Circuit board inspection method, inspection board, and circuit board inspection device | |
| JPS6119142A (en) | Testing device for semiconductor device | |
| JPH05281260A (en) | Inspection system for device on wafer | |
| JPH05347335A (en) | Probe card | |
| JPH0419574A (en) | Inspection jig for printed circuit board | |
| JPH10104301A (en) | Method for inspecting package substrate | |
| JPH0815361A (en) | Inspection method for printed wiring board | |
| JPH07104023A (en) | Printed circuit board inspection method | |
| JPS59174771A (en) | Tester for insulation resistance of circuit board | |
| JPH05315414A (en) | Probe card and inspecting method for its specification | |
| JPH04252964A (en) | Tester head | |
| JPS6137776B2 (en) |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080410 Year of fee payment: 10 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090410 Year of fee payment: 11 |
|
| LAPS | Cancellation because of no payment of annual fees |