JPH0492440A - Method for manufacturing semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To enhance the processing accuracy of a gate by a method wherein an insulating film which is not etched by an etching gas used to process a conductive film is deposited on the conductive film. CONSTITUTION:A first conductive film 3, a second conductive film 4 and an insulating film 5 are deposited sequentially on the whole surface of a substrate 1; then, a photoresist mask 6 for gate processing use is formed on the insulating film 5. The insulating film 5 is composed of an insulating material which is not etched by a fluorine-based etching gas used to dry-etch the conductive film 3 and the conductive film 4. Then, the conductive films 3, 4 and the insulating film 5 are processed sequentially by a dry etching operation; a gate 7 composed of a composite conductive film by a silicide and a high-melting-point metal is formed; and an insulating layer 5a is formed on the gate 7 in a self- aligned manner. At this time, the insulating layer 5a is not etched by the fluorine-based etching gas. Consequently, side-walls of the conductive films 3, 4 can vertically be processed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a manufacturing technology for semiconductor integrated circuit devices, and in particular to MESFET (Multi-Semiconductor MESFET) in which a low resistance semiconductor layer is formed using a selective epitaxial growth method.
ctor Field [1effect Transi
stor).

[Conventional technology]

In order to improve the performance of GaAs MESFETs, metal organic chemical vapor deposition
Mical Vapor Deposition; M
A technique for selectively epitaxially growing a low-resistance semiconductor layer (n''GaAs) on a GaAS substrate using OCV Since a semiconductor layer having a high carrier concentration of about 1018 to 10'/ctl can be obtained, the parasitic resistance of the transistor can be reduced and the speed increase of GaAs MESFET can be promoted.Furthermore, the conventional ion implantation method
In contrast to forming a low-resistance semiconductor layer region in the substrate, the selective epitaxial growth method forms a low-resistance semiconductor layer on the upper layer of the GaAs substrate, so the substrate current is reduced.
This makes it possible to suppress the short channel effect of transistors, thereby reducing the gate length.
High integration of MESFETs can be promoted.

Note that GaAs obtained using the selective epitaxial growth method described above
Examples of literature describing MESFET manufacturing techniques include rGaAs and Related Compounds Symposium ('
l+n protection of n”/n-MOCV
DIInterface and its applic
ation to sidewall assist
d n”GaAs MESFBT” Proc, 1
2th Int, GaAs and rel
Compounds Symp, (198
5) There is J (P2O3).

[Problem to be solved by the invention]

The above conventional technology selectively epitaxially grows a low resistance semiconductor layer on a substrate using a preformed gate as a mask.
k) A low-resistance semiconductor film (n″GaΔS) tends to be abnormally precipitated on the top, which causes a short circuit between the source and drain and a decrease in the interlayer breakdown voltage.
This has the disadvantage that high integration of FETs is hindered.

As a countermeasure, for example, set the Sigh on the gate in advance.
Alternatively, it is possible to prevent abnormal growth of the low resistance semiconductor film on the gate by stacking an insulating layer such as 313N4 and then performing the selective epitaxial growth. The simplest method for laminating the insulating layer on the gate is to deposit a W Six supraperitoneal insulating film for the gate, and pattern the insulating film, WSi, and the film simultaneously during gate processing. However, the etching rate of an insulating film such as S]02 or S l 3 Np with respect to the fluorine-based etching gas used for processing the WSix film is different from that of the WSix film, so when the gate is processed using this method, the sidewalls of the gate become tapered. As a result, the original shape of the gate cannot be obtained. The process increases, but
A conceivable method is to form the gate in advance, deposit the insulating film on the substrate, and then process the insulating film to leave the insulating film only on the gate. However, this method
Since there is a limit to the alignment margin of the mask used for processing the insulating film, it cannot be applied to devices with a gate length of approximately 2 μm or less. Furthermore, this method has the disadvantage that a portion of the gate is unavoidably exposed due to misalignment of the mask, so that the low-resistance semiconductor film is abnormally deposited on the exposed surface of the gate.

As described above, the conventional technique of forming a low-resistance semiconductor layer by selective epitaxial growth using the gate as a mask has not been able to effectively prevent abnormal precipitation of the low-resistance semiconductor film on the gate.

The purpose of the present invention is to form a low-resistance semiconductor layer by a selective epitaxial growth method using a gate as a mask.
The object of the present invention is to provide a technique that can effectively prevent abnormal deposition of a low-resistance semiconductor film on the gate and improve the selectivity of epitaxial growth.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Among the inventions disclosed in this application, a brief overview of typical inventions is as follows.

One invention of the present application is to deposit a conductive film for a gate on a semiconductor substrate, then deposit an insulating film on the conductive film that is not etched by the etching gas used for processing the conductive film, and then combine the conductive film with the insulating film. A gate and an insulating layer stacked thereon are formed by dry etching each film using a different etching gas, and then a low resistance semiconductor layer is selected on the active region of the substrate using the gate and insulating layer as a mask. MESFE grown epitaxially
This is a method for manufacturing T.

Another invention of the present application is to deposit a conductive film made of silicide of a high-melting point metal on a substrate, and then deposit a conductive film made of a high-melting point metal on the conductive film when forming a gate on which the above-mentioned insulating layers are laminated. The insulating film is then deposited on the conductive film made of the high melting point metal to form a gate made of a composite conductive film of the high melting point metal and its silicide.

[Effect]

According to the above-mentioned means, the processing accuracy of the gate is improved by depositing an insulating film on the conductive film that is not etched by the etching gas used for processing the conductive film, so that the side walls of the gate are processed vertically. be able to. In addition, the insulating film and the conductive film are dry-etched using different etching gases to form a gate and an insulating layer stacked thereon in a self-aligned manner. Unlike the method of depositing an insulating film and then processing the insulating film to leave the insulating film only on the gate, a part of the gate is not exposed due to misalignment of the mask, so the exposed surface of the gate is There is no abnormal precipitation of the low resistance semiconductor film.

Furthermore, according to the above-mentioned means, by forming a gate in which a high melting point metal having a lower resistance value than silicide is laminated on silicide, a gate having a lower resistance value than a gate formed of silicide alone can be obtained. , MESFE
It is possible to promote speeding up of T.

〔Example〕

Hereinafter, a method for manufacturing a C, aAsM, ESFET according to this embodiment will be explained with reference to FIGS. 1 to 5.

First, as shown in FIG. 311, silicon, for example, is introduced into the active region of a high-resistance semiconductor substrate 1 made of GaAs by ion implantation, and then the substrate 1 is annealed to form an n-type semiconductor layer 2. A first conductive film 3, for example, is formed on the entire surface of the substrate 1 by sputtering or CVD
A second conductive film 4 and an insulating film 5 are sequentially deposited, and then a photoresist mask 6 for gate processing is formed on the insulating film 5. The first conductive film 3 is made of silicide such as WSlx, and the second conductive film 4 is made of a high melting point metal such as W. The insulating film 5 is made of an insulating material that is not etched by the fluorine-based etching gas used for dry etching the conductive films 3 and 4 during gate processing to be described later. The insulating material that is not etched by fluorine-based etching gas is, for example, aluminum nitride (A ff
l N) or aluminum oxide (AA20.)
It is.

Next, as shown in FIG. 2, the conductive film 3.4 and the insulating film 5 are sequentially processed by dry etching to form a gate 7 made of a composite conductive film of silicide and high melting point metal. Insulating layer 5 in a self-aligned manner
form a. The insulating film 5 deposited on the conductive film 4 is processed by, for example, reactive ion etching (RIE) using a chlorine-based etching gas. The conductive films 3 and 4 are processed by, for example, reactive ion etching (RIE) using a fluorine-based etching gas. When processing the conductive film 3 and the conductive film 4, the insulating film 5 (insulating layer 5a) is not etched by the fluorine-based etching gas. Therefore, unlike the case where an insulating film such as SiO3, Si, N, etc. is used, the sidewalls of the conductive film 3.4 can be processed vertically, so the sidewalls of the obtained gate 7 will not have a tapered shape. do not have.

Next, as shown in FIG. 3, S10. By processing the insulating film 8, such as, by reactive ion etching (RIE), for example, a sidewall spacer 8a is formed on the side wall of the gate 7, and the insulating film 8 on the active region is removed. The n-type semiconductor layer 2 is exposed on the surface of the substrate 1.

Next, as shown in FIG. 4, on the n-type semiconductor layer 2 exposed on the surface of the substrate 1, an n゛゛ semiconductor layer (low resistance semiconductor layer) 9 constituting the source and drain is selected by the MOCVD method. grown epitaxially. At this time, since the insulating film 5 is laminated on the gate 7, the n'' semiconductor film will not be abnormally deposited on the gate 7. Further, since the sidewall spacer 8a is formed on the sidewall of the gate 7, abnormal deposition of the semiconductor film on the sidewall of the gate 7 does not occur. To form the n'' semiconductor layer 9, for example, a mixed gas of trimethyl gallium, arsine, and hydrogen is used, and disilane or hydrogen sulfide is used as the n-type impurity.

Finally, as shown in FIG. 5, an ohmic electrode 10 made of, for example, Au/Ge is formed on the n° type semiconductor layer 9 to form a GaASMESFET.
is completed.

As described above, according to this embodiment, the following effects can be obtained.

(1) After sequentially depositing the conductive films 3 and 4 on the substrate 1, AβN, which is not etched by the fluorine-based etching gas used for processing the conductive film 3.4, is deposited on the conductive film 4.
SA, i! An insulating film 5 such as layer 5a
By selectively epitaxially growing the n-shaped groove conductor layer 9 on the active region of the substrate 1 using the mask as a mask, the insulating layer 5a can be formed on the gate 7 in a self-aligned manner without reducing the processing accuracy of the gate 7. can be formed into As a result, when selectively epitaxially growing the n-shaped groove conductor layer 9 on the active region of the substrate 1, it is possible to reliably prevent the n-shaped semiconductor film from being abnormally deposited on the gate 7. Improves sex.

(2) On the conductive film 3 made of silicide, a second conductive film 4 made of a high melting point metal whose resistance value is lower than that of the silicide is laminated, and a gate 7 made of a composite conductive film of the conductive films 3 and 4 is laminated. By forming the gate 7, the GaAs
MESFET can be made faster.

Above, the invention made by the present inventor has been specifically explained based on the examples, but the present invention is not limited to the above! It goes without saying that the present invention is not limited to the present embodiment, and that various changes can be made without departing from the gist thereof.

In the above embodiment, the gate was constructed of a composite conductive film of WSi and W, but a solicide (M
The gate may be formed of a composite conductive film of a high melting point metal other than W (Mo, Ti, etc.) and a high melting point metal other than W (Mo, Ti, etc.). Furthermore, the gate may be composed of silicide alone or high-melting point metal alone, but if silicide alone is used, there is a disadvantage that high-speed operation cannot be obtained compared to the embodiment. It has the disadvantage of being inferior in terms of Schottky characteristics.

In the above embodiment, AA is used as the insulating layer material laminated on the gate.
Although N or Allos is used, the present invention is not limited thereto, and other insulating materials that are not etched by fluorine-based etching gas may be used.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

(1) After depositing a conductive film for a gate on a semiconductor substrate,
An insulating film that is not etched by the etching gas used to process the conductive film is deposited on the conductive film, and then the insulating film and the conductive film are dry-etched using different etching gases to form a gate and a layer laminated thereon. In the MESF of the present invention, a low resistance semiconductor layer is selectively epitaxially grown on the active region of the substrate using the gate and the insulating layer as a mask.
According to the method for manufacturing an ET, when the low resistance semiconductor layer is epitaxially grown on the active region of the substrate, it is possible to reliably prevent the low resistance semiconductor film from being deposited on the gate. selectivity is improved.

(2) By configuring the gate with a composite conductive film of a high melting point metal and its silicide, it is possible to accelerate the speed of the MESFET.

[Brief explanation of the drawing]

1 to 5 are cross-sectional views of essential parts of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention in order of steps. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... η-type semiconductor layer, 3.4.
... Conductive film, 5, 8... Insulating film, 5a... Insulating layer,
6... Photoresist mask, 7... Gate, 8a.
...Side wall spacer, 9...n° type semiconductor layer (low resistance semiconductor layer), 10...Ohmic electrode. Agent Patent Attorney Katsuo Ogawa Figure 2 (n) Figure 2 (n) 9: n' type semiconductor layer Figure 2 R; I 2 (n) 5a: Insulating film 7: Gate 2 (n)

Claims (1)

[Claims] 1. After depositing a conductive film for a gate on a semiconductor substrate, an insulating film is deposited on the conductive film, and then the insulating film and the conductive film are dry-etched to form the gate and the conductive film. A method for manufacturing a MESFET, comprising forming an insulating layer laminated thereon, and then selectively epitaxially growing a low resistance semiconductor layer for a source and a drain on an active region of the semiconductor substrate using the gate and insulating layer as a mask. A method for manufacturing a semiconductor integrated circuit device, characterized in that the insulating film deposited on the conductive film is an insulating film that is not etched by an etching gas used to process the conductive film. 2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the insulating film deposited on the conductive film is an aluminum nitride film or an aluminum oxide film. 3. After depositing a conductive film made of silicide of a high melting point metal on the semiconductor substrate, depositing a conductive film made of a high melting point metal on the conductive film, and then depositing the insulating film on the conductive film made of the high melting point metal. 3. The method of manufacturing a semiconductor integrated circuit device according to claim 1, further comprising depositing a film.