JPH03220730A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a manufacturing technology for semiconductor integrated circuit devices, and in particular to an M E S F E T (MBtal) method for forming a low resistance semiconductor layer using a selective epitaxial growth method. Se
m1conductor Field Beffect
The present invention relates to technology that is effective when applied to

[Conventional technology]

In order to improve the performance of GaAs MESFETs, metal organic chemical vapor deposition
micaI Vapor Deposition; M
A technique for selectively epitaxially growing a low-resistance semiconductor layer (n"GaAs) on a GaAs substrate using OCVD (OCV D) is being used. According to the selective epitaxial growth method described above, it is possible to selectively epitaxially grow a low resistance semiconductor layer (n"GaAs) on a GaAs substrate. Since a semiconductor layer having a high carrier concentration of about 1018 to 109/cm can be obtained, the parasitic resistance of the transistor can be reduced and the speed increase of GaAs MESFET can be promoted. In contrast to forming a low-resistance semiconductor layer region, the selective epitaxial growth method described above forms a low-resistance semiconductor layer on the upper layer of the GaΔS substrate, thereby reducing the substrate current and thereby suppressing the short channel effect of the transistor. Therefore, the gate length can be shortened, that is, GaAsMES
High integration of FETs can be promoted.

Note that GaAs obtained using the selective epitaxial growth method described above
Examples of literature describing MESFET manufacturing techniques include rGaAs and Related Compounds Symposium ("
Improvement of n+/n-MDCVD
interface and its applica
tion to s+dewall assistec
ln”GaAs MIESFET” Proc, 12
th Int, GaAs and related
Compounds Sym+1. (1985)
J, P505.

[Problem to be solved by the invention]

The above conventional technology selectively epitaxially grows a low resistance semiconductor layer on a substrate using a preformed gate as a mask.
) A low-resistance semiconductor film (n+Ga AS) tends to be abnormally precipitated thereon, which causes a short circuit between the source and the drain and a decrease in interlayer breakdown voltage, which has the drawback of hindering high integration of GaAs MESFETs.

As a countermeasure, for example, 5102
Alternatively, it is possible to prevent abnormal growth of the low resistance semiconductor film on the gate by laminating an insulating layer of Si, N, etc. and then performing the selective epitaxial growth. The simplest method for stacking the insulating layer on the gate is to deposit the insulating film on the WSiX film for the gate, and simultaneously punctuate the insulating film and the WSix film during gate processing. However, 3102 or 3
Insulating films such as 13N+ have an etching rate of 'v' for the fluorine-based etching gas used to process the WSix film.
Since it is higher than the Vsjx film, if the gate is processed using this method, the side walls of the gate will become tapered, and the original shape of the gate will not be obtained.

Therefore, although the number of steps increases, a method can be considered in which the gate is formed in advance, the insulating film is deposited on the substrate, and then the insulating film is processed to leave the insulating film only on the gate. However, this method cannot be applied to devices with a gate length of about 2 μm or less because there is a limit to the alignment margin of the mask used for processing the insulating film. Furthermore, this method has the disadvantage that a portion of the gate is unavoidably exposed due to misalignment of the mask, so that the low-resistance semiconductor film is abnormally deposited on the exposed surface of the gate.

As described above, the conventional technique of forming a low-resistance semiconductor layer by selective epitaxial growth using the gate as a mask has not been able to effectively prevent abnormal precipitation of the low-resistance semiconductor film on the gate.

An object of the present invention is to form a low-resistance semiconductor layer by selective epitaxial growth using a gate as a mask.
The object of the present invention is to provide a technique that can effectively prevent abnormal deposition of a low-resistance semiconductor film on the gate and improve the selectivity of epitaxial growth.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

One invention of the present application includes forming a gate on a semiconductor substrate, forming an insulating layer on the gate in a self-aligned manner, and then using the gate and the insulating layer as a mask to form a layer on the active region of the semiconductor substrate. MESFET, in which a silicon layer (or aluminum layer) is formed in advance in a self-aligned manner on the gate in selective epitaxial growth of a resistive semiconductor layer, and then the silicon layer (or aluminum layer) is oxidized to form the insulating layer. This is a manufacturing method.

Another invention of the present application is that the gate is constructed of a high melting point metal silicide and a composite conductive film of a high melting point metal laminated thereon.

[Effect]

According to the above means, by oxidizing the silicon layer (or aluminum layer) stacked on the gate in a self-aligned manner, an insulating layer is formed on the gate in a self-aligned manner without reducing the processing accuracy of the gate. can do.

Furthermore, according to the above-mentioned means, by forming a gate made of a composite conductive film in which a high melting point metal having a lower resistance value than silicide is laminated on silicide, the resistance value is lower than when the gate is formed using silicide alone. Since a low gate can be obtained, high speed MESFETs can be promoted.

〔Example〕

Hereinafter, G a A s M E S F according to this example
A method for manufacturing ET will be explained with reference to FIGS. 1 to 6.

First, as shown in FIG. 1, silicon, for example, is introduced into the active region of a high-resistance semiconductor substrate 1 made of GaAs by ion implantation, and then the substrate 1 is annealed.
After forming the n-type semiconductor layer 2, a first conductive film 3, a second conductive film 4, and a silicon film 5 are sequentially deposited on the entire surface of the substrate 1 by, for example, a sputtering method or a CVD method, and then the silicon film 5 is deposited on the entire surface of the substrate 1. A photoresist mask 6 for gate processing is formed thereon. The first conductive film 3 is, for example, WSI
The second conductive film 4 is made of silicide such as X.
For example, it is made of a high melting point metal such as W.

Next, as shown in FIG. 2, the conductive film 3.4 and the silicon film 5 are sequentially processed by dry etching to form a gate 7 made of a composite conductive film of silicide and high melting point metal, and the gate 7 is formed on the gate 7. A silicon layer 5a is formed in a self-aligned manner. The conductive film 3.4 and silicon film 5 are processed by reactive ion etching (RIE) using, for example, a chlorine-based etching gas.

Next, as shown in FIG. 3, the gate 7 is etched by processing the insulating film 8, such as 3102, deposited over the entire surface of the substrate 1 by, for example, the CVD method, by, for example, the reactive ion etching (RIE) method. Sidewall spacers 8a are formed on the sidewalls, and the insulating film 8 on the active region is removed to expose the n-type semiconductor layer 2 on the surface of the substrate 1.

Next, as shown in FIG. 4, the silicon layer 5a stacked on the gate 7 is oxidized to form an insulating layer 5b made of S]02. The oxidation treatment of the silicon layer 5a is performed by irradiating the surface of the substrate 1 with ultraviolet rays in an atmosphere containing ozone, for example. Thereby, the insulating layer 5b is formed on the gate 7 in a self-aligned manner.

Next, as shown in FIG. 5, on the n-type groove conductor layer 2 exposed on the surface of the substrate 1, an n+ type groove conductor layer (low resistance semiconductor layer) 9 constituting the source and drain is selected by MOCVD. grown epitaxially. At this time, since the insulating layer 5b is laminated on the gate 7, the n" type semiconductor film will not be abnormally deposited on the gate 7. Also, the side wall spacer 8a is formed on the side wall of the gate 7. Therefore, an n+ type semiconductor film is not abnormally deposited on the side wall of the gate 7. To form the above n+ type groove conductor layer, for example, a mixed gas of trimethyl gallium, arsine, and hydrogen is used to form an n type semiconductor film. Disilane or hydrogen sulfide is used as an impurity.

Finally, as shown in FIG. 6, an ohmic electrode 10 made of, for example, Au/Ge is formed on the n4 type semiconductor layer 9 to form a GaAs MESFET.
is completed.

As described above, according to this embodiment, the following effects can be obtained.

[1) After sequentially depositing conductive films 3 and 4 on the substrate 1, a silicon film 5 is deposited on the conductive film 4, and then the silicon film 5 and the conductive films 3 and 4 are dry-etched to form a gate. After forming an insulating layer 5b by oxidizing the silicon layer 5a, an N4 type semiconductor is formed on the active region of the substrate 1 using the gate 7 and the insulating layer 5b as a mask. By selectively epitaxially growing the layer 9, the insulating layer 5C can be formed on the gate 7 in a self-aligned manner without reducing the processing accuracy of the gate 7. As a result, when selectively epitaxially growing the n-type semiconductor layer 9 on the active region of the substrate 1, it is possible to reliably prevent the n-type semiconductor film from being abnormally deposited on the gate 7. Improves sex.

(2) On the conductive film 3 made of silicide, a second conductive film 4 made of a high melting point metal whose resistance value is lower than that of the silicide is laminated, and a gate 7 made of a composite conductive film of the conductive films 3 and 4 is laminated. By forming the gate 7, the GaAs
MESFET can be made faster.

Although the invention made by the present inventor has been specifically explained based on Examples above, the present invention is not limited to the above Examples, and various modifications can be made without departing from the gist thereof. Needless to say.

In the above embodiment, a silicon film is deposited on the conductive film, and then the silicon film is oxidized to form an insulating layer on the gate, but the invention is not limited to this. For example, an aluminum film is deposited on the conductive film. may be deposited, and then the aluminum film is oxidized to form an insulating layer made of aluminum oxide on the gate.

In the above embodiments, the insulating layer was formed on the gate by irradiating the surface of the substrate with ultraviolet rays in an ozone-containing atmosphere, but the insulating layer is not limited thereto. An insulating layer may be formed on the gate by thermally oxidizing the insulating layer.

In the above example, the gate was constructed using a composite conductive film of WSiX and W(II), but a silicide other than WSiX (
The gate may be formed of a composite conductive film of a high melting point metal (Mo, Ti, etc.) other than W (MoSiX, Ti5iX, etc.) and a high melting point metal other than W (Mo, Ti, etc.). In addition, the gate may be composed of silicide = 12- alone or a high-melting point metal alone, but when using silicide alone, there is a disadvantage that high-speed operation cannot be obtained compared to the embodiment, and when using only a high-melting point metal, There is a disadvantage that the Schottky characteristics are inferior to those of the examples.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

[l) After forming a gate on a semiconductor substrate and forming a silicon layer (or aluminum layer) on the gate in a self-aligned manner, the silicon layer (or aluminum layer) is oxidized to insulate it. According to the MESFET manufacturing method of the present invention, the low resistance semiconductor layer is selectively epitaxially grown on the active region of the semiconductor substrate using the gate and insulating layer as a mask. When epitaxially growing a semiconductor layer, it is possible to reliably prevent a low-resistance semiconductor film from being abnormally deposited on the gate, thereby improving the selectivity of the epitaxial growth.

(2) By configuring the gate with a composite conductive film of a high melting point metal and its silicide, it is possible to accelerate the speed of the MESFET.

[Brief explanation of drawings]

1 to 6 are cross-sectional views of essential parts of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention in order of steps. 1... Semiconductor substrate, 2... N-type semiconductor layer, 3.4.
... Conductive film, 5... Silicon film, 5a... Silicon layer, 5b... Insulating layer, 6... Photoresist mask,
7... Gate, 8... Insulating film, 8a... Side wall spacer, 9... n'-type semiconductor layer (low resistance semiconductor layer), 10... Electrode. 177 nL

Claims (1)

[Claims] 1. After forming a gate on a semiconductor substrate and forming an insulating layer on the gate in a self-aligned manner, the active region of the semiconductor substrate is formed using the gate and the insulating layer as a mask. A method for manufacturing a MESFET, including a step of selectively epitaxially growing a low resistance semiconductor layer, the method comprising forming a silicon layer on the gate in a self-aligned manner, and then oxidizing the silicon layer to form the insulating layer. A method for manufacturing a semiconductor integrated circuit device, characterized by: 2. Instead of forming a silicon layer on the gate in a self-aligned manner, forming an aluminum layer on the gate in a self-aligned manner, and then oxidizing the aluminum layer to form the insulating layer. 2. The method of manufacturing a semiconductor integrated circuit device according to claim 1. 3. Claim 1, wherein the oxidation treatment is performed by irradiating ultraviolet rays in an atmosphere containing ozone.
or 2. The method for manufacturing a semiconductor integrated circuit device according to 2. 4. The method of manufacturing a semiconductor integrated circuit device according to claim 1, 2 or 3, wherein the gate is made of a composite conductive film of a high melting point metal silicide and a high melting point metal layered thereon.