JPH049343B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a device for recording and displaying the passing addresses of an executed program in order to inspect, evaluate and debug a computer program. The present invention relates to an apparatus that enables efficient debugging by making it possible to easily determine whether the address corresponding to a branch is taken or not taken.

[Conventional technology]

Performs inspection and evaluation of computer programs,
When correcting errors, that is, debugging, the same program is repeatedly executed while setting various conditions such as input data values, and the address information of the steps it passes is sequentially recorded (trace). Therefore, it is necessary to grasp the execution status of the program, including checking whether there are any steps that have not been passed. One method for performing such tracing is to install a program trajectory recording device (tracing device) that has a memory that has a memory location that corresponds one-to-one to the address of each step of the program, and to When a system (such as a system) specifies an address and reads and executes a program step by step, address information about the specified address is sequentially taken into the program passage recording device, and the memory corresponding to the address is stored in the memory. A method has already been proposed in which a passage indication is written at a location (Patent No.
1134367). An example of a passage display written to the memory using this method is shown in Figure 2. In this example, passage display "1" is written from address "0001" to "0004" and "0006". , it is shown that these steps have been executed, whereas the address “0005” has a passing indication “1”.
has not been written, indicating that this step has not been executed.

[Problem that the invention seeks to solve]

By the way, when the tracing method described above is used, in a program including a branch instruction, as shown in FIG. When the step “0003” exists, the memory address “0002”, “0003”
By examining the passage display of the position corresponding to
It is possible to immediately determine whether a branch instruction is passed under the conditions of a branch taken or not taken (or whether both are passed). However, as illustrated in Fig. 3b, one of the branch destinations of the step at address "0001" corresponding to the branch instruction (failure side)
There is a step with address “0002”, but
On the other hand (on the side where the branch is established), if there is no step and the branch ends and the step goes directly to the step at address "0003", then "0003" of the locations corresponding to addresses "0002" and "0003" in the memory is ”
If a passage indication is written only at the position corresponding to address “0002” and “0003”, it can be confirmed that the branch instruction has been passed only under the condition that the branch is taken. If it is included,
It becomes impossible to determine whether the branch instruction is passed only under the condition that the branch is not taken, or whether both conditions are passed.

For this reason, with this tracing method, the execution state of a program including branch instructions may not be accurately grasped, and this poses a problem in that it is an impediment to realizing efficient debugging.

This invention was made in view of the above points,
It is an object of the present invention to provide a trace device that can efficiently debug programs containing branch instructions.

[Means for solving problems]

A program passage address tracing device according to the present invention includes at least two series of storage means each having a storage location corresponding one-to-one to each address of a program, and a system for tracing address information between adjacent steps in an executed program. Based on
a determining means for determining whether a branch is taken or not taken for each step; a selecting means for selecting one of the series in the storage means according to the determination of whether the branch is taken or not taken in the determining means; and in the selected series, a writing means for writing predetermined passage display information into a storage location corresponding to the address information of the step related to the determination; a means for reading out the stored contents of the storage means; and a reading means for reading from the storage location of each series corresponding to the same address. a designating means for designating display content for the address in accordance with a combination of stored memory contents, and a displaying means for displaying a predetermined display indicating the passing state of each address of the program based on the designation by the designating means. It is characterized by

[Effect]

Once the tracing device is given address information,
Depending on whether the branch is established or not, different series of storage means are selected, and passage display information is written into the corresponding storage location within the selected series. As a result, passage display information is stored in corresponding storage locations of different series when the address is passed under the condition that the branch is taken and when the address is passed under the condition that the branch is not taken. Therefore, depending on the combination of the storage contents (presence or absence of passage display information) of the memory locations in each series corresponding to the same address, the passage status (passed or not) and branch status (only the conditions for branch establishment) of the address can be determined. By displaying the passage based on the display contents specified according to this combination, the passage status of the address can be determined. Not only this, but also the branching situation can be easily judged.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a diagram showing an embodiment of a program passing address tracing device according to the present invention. The tracing device 1 is connected to a device under test 16 (such as a computer system) via an interface 19. As shown in FIG. The device under test 16 includes a microcomputer 17 and a memory 18.
8 includes a program area for recording programs executed by the microcomputer 17 and an I/O (input/output data) area. Address information of each address in the memory 18 accessed by the microcomputer 17 (i.e., execution address signal a indicating the absolute address of each accessed address (execution address)) and function information (i.e., each execution address is connected to the program area and I/O). A function signal b) that distinguishes which area of the O area it belongs to, and further distinguishes whether it corresponds to upper data or lower data if it belongs to the I/O area. is provided to the tracing device 1 via the interface 19.

According to this invention, the trace device 1 is provided with a branch instruction determination circuit 2, and the branch instruction determination circuit 2 receives the address information, that is, the execution address signal a given to the trace device 1, via the gate circuit 20. Enter. The control input of the gate circuit 20 is connected to the output line L1 of the decoder 5. When the function signal b has content indicating that the execution address belongs to the program area, a signal "1" is generated on the output line L1, and at this time, the gate circuit 20 is opened and the program area corresponding to the function signal b is executed. Address signal a is input to branch instruction determination circuit 2. As a result, only the execution address signal a of the program area is input to the determination circuit 2.

The determination circuit 2 determines whether or not a branch is established for an execution address corresponding to a branch instruction based on the presence or absence of an address jump in the execution address signal a of an adjacently inputted program area, as shown in FIG. It includes registers 21 and 22, an adder 23, and a comparator 24. The execution address signal a input to the determination circuit 2 is applied to the register 21, and is taken into the register 21 at the timing of the clock pulse φ. The output of register 21 is
is applied to the comparator 24 and the register 22
and is taken into the register 22 at the same timing of the clock pulse φ. The output of register 22 is applied to comparator 24 via adder 23. The adder 23 adds a numerical value "1" to the value of the input address signal. Comparator 24
compares the values of the two input address signals,
It outputs a signal indicating the comparison result as to whether or not the two match.

The conditions of the output line L1 of the decoder 5 and the execution address signal a1 which is the processing clock are stored in the register 21.
When the signal a1 is taken in to the next output line L1 condition and processing clock, the signal a1 is taken into the register 22, and the adder 23 adds "1" to the value and gives it to the comparator 24. The next execution address signal a2 is taken in, and the comparator 2
given to 4. At this time, the comparator 24 compares the values of the two input signals (signal a1 plus "1" and signal a2), and if they do not match due to the presence of an address jump (for example, a1 = “0001”, a2 = “0003”) A comparison result signal to that effect is output, and if the addresses are consecutive and both match (for example, a1 = “0001”, a2 =
“0002”) Outputs a comparison result signal to that effect. Thereafter, the above-described comparison process is repeated in the same manner for execution address signals a of program areas that are input adjacent to each other.

Furthermore, the conditions taken into the registers 21 and 22 are as follows:
It is updated only when the conditions of the output line L1 of the decoder 5 and the processing clock are met.

Among the comparison result signals output from the comparator 24, a comparison result signal indicating that the two input signals do not match (this is set as "1") is sent from the determination circuit 2 to the selector 3 as a branch establishment signal. It is applied to the selected input A. In addition, a comparison result signal indicating that the two input signals match (this is set as "0") is sent from the determination circuit 2 via the inverter 4 to the selected input of the selector 3 as a branch failure signal.
given to A′.

On the other hand, of the address information given to the trace device 1, the function signal b is input to the decoder 5. The decoder 5 decodes the input function signal b and generates a signal on one of the output lines depending on its content. That is, when the signal b indicates that the execution address belongs to the program area, a signal "1" is generated on the output line L1 connected to the selection input S of the selector 3 and the control input of the gate circuit 20. Further, when the signal b indicates that the execution address corresponds to upper data in the I/O area, a signal "1" (upper data signal) and indicates that the execution address corresponds to lower-order data in the I/O area, a signal “1” (lower-order data signal).

The selector 3 selects and outputs the signals input to the selected inputs A and A' when a signal "1" is applied to the selection input S, and when the signal "1" is not applied to the selection input S. At this time, the signals input to the selected inputs B and B' are selected and output. That is, when the decoder 5 generates a signal "1" on the output line L1 connected to the selection input S (that is, when the function signal b indicates that the execution address belongs to the program area), , when a branch established signal is applied to the selected input A from the determination circuit 2, the selector 3 selects and outputs this branch established signal. In the above case, when the branch failure signal is applied from the determination circuit 2 to the selected input A', the selector 3 selects and outputs this branch failure signal. Further, when the decoder 5 generates a signal "1" (upper data signal) on the output line L2 connected to the selected input B (signal b indicates that the execution address corresponds to upper data in the I/O area). (in the case shown), the selector 3 selects and outputs this upper data signal applied to the selected input B. When the decoder 5 generates a signal "1" (lower data signal) on the output line L3 connected to the selected input B' (signal b indicates that the execution address corresponds to lower data in the I/O area) case), the selector 3 selects and outputs this lower data signal applied to the selected input B'.

Among the signals selected and output from the selector 3, the branch established signal given to the selected input A and the upper data signal given to the selected input B are sent to the control input of the gate circuit 8 via the AND circuit 6. The branch failure signal applied to the selected input A' and the lower data signal applied to the selected input B' are applied to the control input of the gate circuit 9 via the AND circuit 7.

In addition to the signal output from the selector 3, the AND circuits 6 and 7 are supplied with a write timing signal and a trace signal, respectively. The write timing signal controls the timing when the passage display of the address accessed by the microcomputer 17 is written to the memory in the trace device 2. The trace signal is obtained by ANDing the trace range designation signal c and start/stop signal d outputted from the condition setting circuit 10 in an AND circuit 11. The condition setting circuit 10 holds in advance information about the address range to be traced among all the addresses in the memory 18, and inputs the execution address signal a to set each signal a.
It is determined whether or not it belongs to this address range, and if it belongs to the address range, it outputs "1" as the trace range designation signal C. Further, the condition setting circuit 10 can set a specific range in the memory 18 as a trace range depending on the specific situation, and if the input signal a belongs to this set trace range, the above-mentioned Outputs "1" as the start/stop signal d. Therefore, when the input execution address signal a is included in both the address range and the trace range, the condition of the AND circuit 11 is satisfied, and the signal "1" (trace signal) is sent to the AND circuits 6 and 7. is given.

When the selector 3 selects and outputs the branch established signal or the upper data signal and the write timing signal and trace signal are applied to the AND circuit 6, the gate circuit 8 is opened.
Further, when the selector 3 selects and outputs the branch failure signal or the lower data signal, and the write timing signal and the trace signal are applied to the AND circuit 7, the gate circuit 9 is opened.

A memory chip select signal a _x is applied to gate circuits 8 and 9 from a memory chip select circuit 14 . The memory chip select circuit 14 receives an execution address signal a given from the device under test 16.
is input, and the memory chip corresponding to each execution address is selected from the memory in the trace device 2 in which the passage display is to be written, and the memory chip select signal a _x is a signal indicating the selection content.

According to this invention, the program area and I/O
Two trace memories 12 and 13 are provided in the trace device 2 as memories that have memory locations that correspond one-to-one to each address of the area, and in which passing indications are written. The memory chip select signal a _x outputted from the memory chip select circuit 14 is given to the trace memory 12 via the gate circuit 8 and also to the gate circuit 9.
The signal is applied to the trace memory 13 via.

Further, the memories 12 and 13 are given a memory address signal _ay from a memory address circuit 15. The memory address circuit 15 inputs the execution address signal a and specifies the address on the memory chip in the memories 12 and 13 corresponding to each execution address, and the memory address signal _ay is a signal indicating the specified contents. be.

In the memories 12 and 13, one address is specified by the combination of the memory chip select signal a _x and the memory address signal a _y (in other words, one bit of memory location corresponding to one specific execution address is ) Passage display information (that is, one bit of signal "1") is written.

Thereby, the function signal b indicates that the execution address belongs to the program area, and the determination circuit 2 gives a branch established signal to the selector 3 based on the existence of an address jump of the execution address, or is a case where signal b indicates that the execution address corresponds to upper data in the I/O area, and when the write timing signal and trace signal are given to the AND circuits 6 and 7, the execution The storage location in _the memory 12 corresponding to the address is specified by a combination of the memory chip select signal _a
is written. Further, the signal b indicates that the execution address belongs to the program area, and the determination circuit 2 gives a branch failure signal to the selector 3 based on the consecutive execution addresses, or the signal b indicates that the execution address corresponds to lower data in the I/O area, and when the write timing signal and the trace signal are given to the AND circuits 6 and 7, the execution address corresponds to the execution address. Passage display information (signal "1") is written in the storage location of the memory 13 in the same manner as described above.

Memory 1 corresponding to the program area address
The stored contents of the storage locations 2 and 13 corresponding to the same address are sequentially read out in parallel by the microcomputer 25 in the trace device 1 and provided to the display designation circuit 26. The display designation circuit 26 selects the memory 1 corresponding to the same address.
Based on the combination of the presence/absence of passage display information "1" in the storage locations 2 and 13, the passage status and branch status of the address during program execution are determined.

An example of the configuration of the display designation circuit 26 is shown in FIG. The NOR circuit 27 includes memories 12 and 1.
The memory contents of 3 are given. The AND circuit 28 is supplied with the stored contents of the memory 12 inverted by the inverter 31, and is also supplied with the stored contents of the memory 13. The AND circuit 29 is given the memory contents of the memory 12 and the memory 1
The stored contents of No. 3 are inverted by an inverter 32 and provided. The AND circuit 30 includes a memory 12,
13 memory contents are given. Therefore, the memory 12,1 corresponding to a certain address in the program area
If the passing display information "1" is not stored in the memory locations in 3 (that is, if the address has not passed), only the condition of the NOR circuit 27 is satisfied in the display specifying circuit 26, and the output line A signal "1" is generated only in L4. When the passing display information "1" is not stored in the storage location in the memory 12 and the passing display information "1" is stored in the storage location in the memory 13 (that is, the address is set only under the condition that the branch is not taken). If the address passes (including the case where the address does not correspond to a branch instruction), only the condition of the AND circuit 28 is satisfied, and a signal "1" is generated only on the output line L5.
When the passing display information "1" is stored in the storage location in the memory 12 and the passing display information "1" is not stored in the storage location in the memory 13 (that is, the address is set only under the condition that the branch is established). (in the case of passing), only the condition of the AND circuit 29 is satisfied, and a signal "1" is generated only on the output line L6. When the passage display information "1" is stored in both the memory locations in the memories 12 and 13 (that is, when the address is passed under both conditions of branch taken and branch not taken), only the condition of the AND circuit 30 is stored. is established, and a signal "1" is generated only on the output line L7.

Each output line L4 to L of this display designation circuit 26
7 is a display device 33 (for example, a CRT display)
are connected to control inputs C1 to C4, respectively. The display device 33 sequentially displays each address of the program under the control of the microcomputer 25 while displaying different contents depending on which of the control inputs C1 to C4 is given the signal "1". This is to display the passage. As a result, for each address of the executed program, different display contents are designated by the display designating circuit 26 depending on the passing status and branching status, and the passing display according to the designated contents is performed by the display device 33.

Note that the stored contents of the corresponding storage locations in the memories 12 and 13 for each address in the I/O area are also sequentially read out from the memories 12 and 13 and displayed, but the display is performed using a well-known method. This is something that is done and will not be explained here.

Next, an example of address passing display by this trace device 1 will be explained with reference to FIGS. 6 to 8. FIG. 6 shows the memory 18 in the device under test 16.
2 is a flowchart schematically illustrating a portion of a program stored in the . Path α and path β indicate execution paths when the program is executed twice by the microcomputer 17 under different conditions. Here, in path α, after passing through the step at address "00", it passes through the step at address "01" under the condition that the branch is taken, jumps to address "05", and passes through the step at address "05". ing. Therefore, in this execution, address “01”
Branch taken and addresses “00” and “05”
The determination circuit 2 determines whether the branch is not taken, and based on this, the storage location in the memory 12 corresponding to the address "01" and the addresses "00" and "05" are determined.
The passage display information "1" is written to the storage location in the memory 13 corresponding to the . Next, in path β, the process passes through the step at address "00", passes through the step at address "01" under the condition that the branch is not taken, passes through the step at address "02", and then branches at the step at address "03". It passes under the condition of establishment, jumps to address "05", and passes through the step of address "05". Therefore, in this execution, the determination circuit 2 determines whether the branch is taken for address "03" or the branch is not taken for addresses "00" to "02" and "05", and based on this, the memory corresponding to address "03" is determined. The passing display information "1" is overwritten in the storage locations in the memory 12 and the storage locations in the memory 13 corresponding to the addresses "00" to "02" and "05". Therefore, as a result of these two executions, passage display information "1" is stored in the memory locations in the memories 12 and 13 corresponding to addresses "00" to "05", respectively, as shown in FIG. Become.

Among the memory locations in the memories 12 and 13 corresponding to addresses "00" to "05", the memory contents of the memory location corresponding to address "00" are first read out by the microcomputer 25 and provided to the display designating circuit 26. When the pass display information “1” is stored only in the storage location in the memory 13 for the address “00” (that is, the address “00”
is passed only under the condition that the branch is not taken (FIG. 7), so the designation circuit 26 generates a signal "1" on the output line L5. Therefore, at this time, the display device 3
Signal “1” to C2 among the control inputs C1 to C4 of 3.
is given, and the display device 33 displays the address "00" using a display corresponding to this (for example, "1").
Passage display will be performed. Next, when the storage contents of the storage locations in the memories 12 and 13 corresponding to the address "01" are read out and given to the designation circuit 26, passage display information "1" is stored in both of these storage locations. (i.e. address “01”
(see FIG. 7), the designation circuit 26 generates a signal "1" on the output line L7. Therefore, at this time, a signal "1" is given to the control input C4 of the display device 33, and the display device 33 uses a display corresponding to this (for example, "*") to display the passage for the address "01". Do this. Thereafter, in the same manner, for each of the remaining addresses "02" to "05", the storage contents of the corresponding storage locations in the memories 12 and 13 are sequentially given to the designation circuit 26, and the contents according to the designation of the designation circuit 26 are sequentially applied. The display device 33 displays a passage display using a display of
will do it. (For example, a signal “1” is input to the control input C1.
is given (that is, when the passing display information "1" is not stored in the corresponding storage locations in the memories 12 and 13 because the address has not been passed yet), the display of "・" is used. , when the signal “1” is given to the control input C3 (i.e.,
If the address is passed only under the condition that the branch is established, and the passing display information "1" is stored only in the corresponding storage location in the memory 12, ">"
Use the display. ) Address “00” ~
The passage display for "05" is shown in FIG. According to this passage display, each address "00" to "05" of the program shown in FIG. 6, which was executed twice, was not passed.
At a glance, you can accurately determine whether the test passed only with the condition that the branch was not true, only with the condition that the branch was true, or both. can be judged.

As described above, according to the tracing device 1, it is possible to easily, quickly and accurately judge the passing status and branching status of each address of the executed program based on the content of the passing display on the display device 33. become.

As an additional function, the memory 12, 13 also determines whether each address of the I/O area in the memory 18 accessed during the program execution process corresponds to upper data or lower data. This can be easily done by displaying the presence or absence of the passage display information "1" in the corresponding storage location within.

In this embodiment, the display designation circuit 26 is constituted by a logic circuit as shown in FIG.
It may also be configured by a program within.

Further, in this embodiment, two systems of trace memories 12 and 13 are provided as memories having storage locations corresponding one-to-one to each address of the program, corresponding to each case of a branch being taken or not taken. In order to be able to write the passage display information in different memories depending on the difference in the form of the branch when a branch is established, three or more systems of memories having the above-mentioned storage locations are provided as a whole. It may be something that has been In that case, the display specification circuit 26 also specifies different display contents depending on the difference in the branching mode, etc., so that the display device 33 can display different passage displays according to the difference in the mode, etc. shall be able to do so.

Note that the display device 33 is a CRT display,
Any display means may be used, such as a printer or an optical display panel.

〔Effect of the invention〕

As described above, according to the program passage address tracing device according to the present invention, for each address of an executed program, it is possible to determine not only whether or not the program has passed, but also whether it has passed only under the condition that the branch is taken, or only under the condition that the branch is not taken. It is possible to easily, quickly and accurately judge whether the vehicle has passed through the vehicle or both of the vehicles based on the content of the transit display on the display means. Therefore, it is possible to reduce the burden on the operator and efficiently and accurately debug programs containing branch instructions.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a program passing address tracing device according to the present invention, and FIG. 2 is a diagram showing an example of passing display information of each address written in a memory by a conventional tracing method.
Figures 3a and 3b are diagrams showing typical flowcharts of branch points in a program executed by the device under test;
The figure is a block diagram showing a detailed example of the branch instruction determination circuit in the embodiment of FIG. 1, FIG. 5 is a block diagram showing a detailed example of the display designation circuit in the embodiment, and FIG. FIG. 7 is a flowchart partially schematically showing an example of a program executed in the device under test according to the embodiment; FIG. Diagrams showing information;
FIG. 8 is a diagram showing an example of a passing display performed for each address of the program in FIG. 6 by the display device of the same embodiment. DESCRIPTION OF SYMBOLS 1...Trace device, 2...Branch instruction determination circuit, 3...Selector, 4...Inverter, 5...
Decoder, 6, 7, 11...AND circuit, 8,
9, 20...Gate circuit, 10...Condition setting circuit, 12, 13...Trace memory, 14...Memory chip select circuit, 15...Memory address circuit, 16...Device under test, 17...Microcomputer , 18...Memory, 19...Interface, 21, 22...Register, 23...
Adder, 24...Comparator, 25...Microcomputer, 26...Display designation circuit, 27...NOR circuit, 28-30...AND circuit, 31, 32...
...Inverter, 33...Display device.

Claims (1)

[Scope of Claims] 1. A program passing address tracing device for sequentially receiving address information of a computer program being executed and recording passing addresses of the program, which correspond one-to-one to each address of the program. at least two series of storage means each having a memory location; a determination means for determining whether a branch is taken or not taken for each step based on the relationship of address information between adjacent steps in the executed program; and a branch in this determination means. a selection means for selecting one of the series in the storage means according to a determination of whether the step is established or not; and, in the selected series, predetermined passage display information is stored in a storage location corresponding to address information of a step related to the determination. A writing means for writing, a means for reading out the stored contents of the storage means, and a specifying means for specifying the display contents for the address according to the combination of the stored contents read from the storage locations of each series corresponding to the same address. A program passing address tracing device comprising: a display means for displaying a predetermined display indicating a passing state of each address of the program based on the designation by the designation means. 2. The specifying means corresponds to the presence or absence of passage display information in a storage location corresponding to a certain address of the program in a series where writing is performed when a branch is taken, and the address within the series where writing is performed when a branch is not taken. Claim 1, which specifies four different display contents depending on the combination of presence/absence of passage display information in a storage location.
Program passing address tracing device described in Section 2.