JPH04939A - Method and circuit for processing packet - Google Patents

Abstract

PURPOSE:To increase the processing speed and to quickly report the state of a communication node by successively delaying packets by a time M/N (M is the transmission time per packet and N is a natural number) to fetch N packets in parallel. CONSTITUTION:The transmission time per transfer packet is defined as M, and packets coming from a transmission link 1 in series are distributed and successively written in FIFOs 2a to 2n. N packets successively delayed by the time M/N are outputted from FIFOs 2a to 2n onto information lines 1a to 1n in parallel. That is, packets are successively shifted by the header processing time and made parallel and are not stored with one packet as the unit to perform the header processing. Thus, the packet processing delay in the communication node is shortened, and the state of the communication node is quickly transmitted to another node.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention provides a system in which, in each of a plurality of communication nodes connected to a ring-shaped or bus-shaped transmission link, packets being transferred on the transmission link are automatically transmitted. Packets destined for a node are processed to be received, packets that should be forwarded to another node are processed to be relayed, and packets sent from the own node are sent to the transmission link if there is space on the transmission link. The present invention relates to a packet processing method and circuit.

(Prior Art) Conventionally, methods for transmitting and receiving packets based on control information and address information written in the header of received packets include packet communication according to CCITT Recommendation The method and
There is a slotted ring type communication system (for example, a reset type communication system, see Japanese Patent Application No. 1-144534).

Packet processing circuit configurations in communication nodes include those in which packets that arrive at the communication node are stored once and then processing is started, and even if the processing that started at the same time the packet arrives ends, the next packet still arrives. Generally, the process is stopped until this point.

[Problem B to be solved by the invention] However, in the storage-type processing method described above, the time it takes to complete packet storage is longer than the original header processing time (
This is necessary in addition to the processing performed based on the control information and address information written in the header, and in a communication system where many communication nodes are connected on a transmission link, it is necessary to There is a problem in that packet transfer delays with terminals accommodated in other communication nodes become large, and in a method that starts processing as soon as the packet arrives, processing is performed based on the access control information of the received packet. Even if the state transition processing is completed, the state of the communication node after the state transition cannot be notified to other communication nodes until it is written in the access control information area of the next received packet and sent. There was a problem.

The purpose of the present invention is to solve the problems of the prior art,
By reducing the number of packet processing circuits in a communication node and making it possible to process the next header without stopping processing after completing header processing, the status of a communication node can be quickly communicated to other communication nodes. An object of the present invention is to provide a packet processing method and circuit in a communication node that can make notifications.

[Means to solve the problem]

To achieve the above object, in the present invention, in each of a plurality of communication nodes connected to a ring-shaped or lotus-shaped transmission link, a packet including a user information area, an address information area, and an access control information area is transmitted on the transmission link. If the packet is destined for the own node, it is processed to receive it, and if it is a packet that should be forwarded to another node, it is processed to be relayed, and if there is free space on the transmission link. For example, a bucket/node process that executes the process of transmitting a transmission packet from its own node onto a transmission link by referring to the address information and access control information for each packet transferred on the transmission link. In the circuit, the time required for transmission on the transmission line per packet is M
When the time required to process one packet at the communication node is M/N (N is a natural number),
A parallelization circuit that parallelizes and captures N packets transmitted serially on a transmission link with a delay of (M/N) time each, a delay circuit with N inputs and N outputs, and a delay circuit with N inputs and 1 output. The apparatus included a reception buffer, a reception processing circuit, a transmission buffer, a transmission processing circuit, a multiplexing circuit, and a header processing circuit.

[Effect]

When the time required to transmit one packet on the transmission path is M, the time required to process one packet at the communication node is M/N (where N is a natural number), and the time required to transmit one packet on the transmission path is M/N. N incoming packets are processed in parallel with a delay of (M/N) time for each packet, and are taken in for continuous processing.After processing, they are returned to serial form and sent out on the transmission link.

〔Example] Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a block diagram showing an example of the configuration of a communication system to which the present invention is implemented. Communication node 10a-10
d is connected to the transmission line 1 which is a ring-shaped transmission link, and packet communication is performed between them.

FIG. 3 is a configuration diagram of a transfer packet used in an embodiment of the present invention. As seen in the figure, a transfer packet is composed of a fixed-length packet header consisting of an access control information area (ACF area) and an address information area, and a fixed-length user information area.

FIG. 1 is a block diagram showing the configuration of a communication node as an embodiment of the present invention. In FIG. 1, ■ is a transmission link, 2 is a parallelization circuit that parallelizes packets arriving from the transmission link by M/N time between the transmission links by N parallelization, 1a to 1n are parallelized information lines, 3 is a multi-electrification circuit that sends packets to the transmission link, and 4 is a circuit that corresponds to the time required for header processing and 43 to 4n for parallelized information lines.
5 is a delay circuit that delays packets, and 5 is an N input l that performs buffer pulling from 5a to 5n corresponding to parallelized information lines.
An output reception buffer 6 copies and transfers the packet sent from the parallelization circuit 2 to both the delay circuit 4 and the reception buffer 5, and also copies access control information and address information from the packet header and transfers it to the header processing circuit 8. A reception processing circuit 7 stores packets to be sent from a terminal (not shown) to a transmission link from a terminal (accommodated in the communication node) in a single buffer, and parallelizes the packets by a signal from the header processing circuit 8. 8 is a header processing circuit that performs packet transmission/reception determination and state transition processing, and 9 is a transmission processing circuit that is controlled by a signal from the header processing circuit.

FIG. 4 is an explanatory diagram showing the arriving packet parallelization mechanism in the parallelization circuit 2 in FIG. 1. In Figure 4,
2a, 2b, . . . 2n are each FIF○ (first in first out).

A packet processing procedure as an embodiment of the present invention will be described with reference to FIGS. 1 and 4.

(b) First, packets that arrive at the parallelization circuit 2 via the transmission link 1, which is a transmission path, are sequentially distributed and transferred to the FIFOs 2a to 2n, and are
As shown in the figure, the data is output while being parallelized.

In other words, a transfer packet arriving via transmission link 1, which is a transmission path, is transferred to the FIFO by a write clock of period A.
2a to 2n, and from each FIFO, N pieces of data are read out in parallel and output from each FIFO using a read clock with a period of A/N. Here, N is an arbitrary natural number.

Here, the time required to transfer one transfer packet is M
Then, by distributing packets that arrive serially on transmission link 1 to FIFOs 2a to 2n and writing them sequentially, packets delayed by (M/N) time from each of FIFOs 2a to 2n are written to N The data are output in parallel onto the information lines 1a to ln.

(b) Of the next parallelized packets, the packets on the information line la are first transferred to the reception processing circuit 6, and the reception processing circuit 6 receives each packet in correspondence with the information line while duplicating the packets. It is transferred to both the amplifier 5 and the delay circuit 4. Further, the reception processing circuit 6 also copies the access control information and address information that constitute the header of the packet and transfers it to the header processing circuit 8.

(c) Based on the address information of the packet transferred from the reception processing circuit 6, the header processing circuit 8 determines whether the arriving packet transferred on the information line la is addressed to the terminal connected to its own communication node. It is determined whether the packet is a packet or not, and if the packet is addressed to a terminal connected to the own communication node, a reception permission is notified to 5a in the reception buffer 5 (hereinafter referred to as
(referred to as reception permission signal).

(d) In parallel with the processing in (c) above, the header processing circuit 8 determines the final destination of the arriving packet being transferred on the information line la based on the address information transferred from the reception processing circuit 6. It is determined whether the packet is the own communication node or not, and if the final destination of the packet is the own communication node, the transmission buffer 7 is notified of permission to transmit the stored packet to the information line 1a (hereinafter referred to as 1a transmission permission). It also notifies the transmission processing circuit 9 that the packet being transferred on the information line la is a packet that does not need to be relayed to the next communication node (hereinafter referred to as a transmission type signal). )do.

To supplement the explanation, even if the arriving packet transferred on the information line 1a is destined for a terminal connected to the own communication node as described above, the final destination is the own communication node as is. It's not necessarily a packet. For example, there is a broadcast-type relay packet, which is a packet that should be forwarded to all communication nodes, so it is a packet addressed to the terminal connected to its own communication node, and at the same time, it is also a packet addressed to other communication nodes. This is the packet that should be transferred.

On the other hand, if a packet is to be transferred between one communication node on a one-to-one basis, and if it is a packet destined for a terminal connected to the own communication node, then the packet is destined for the own communication node as the final destination. Become.

The header processing circuit 8 makes this determination based on the address information, and if it is determined that the packet does not need to be relayed to the next communication node, a corresponding amount of free space will be created in the communication path on the information line la. Therefore, the communication node decides to transmit the packet to be transmitted that has been kept in the transmission buffer 7 of its own communication node, and notifies the transmission buffer 7 of the transmission permission signal to that effect.

(e) Based on the transmission permission signal from the header processing circuit 8, the transmission buffer 7 starts transferring the buffered packet to the transmission processing circuit 9 via the information line 1a.

(f) In parallel with the above-mentioned processes (c) and (d), the header processing circuit 8 performs state transition processing based on the access control information transferred from the reception processing circuit 6 and the internal state of its own communication node. new access control information is generated based on the state after the transition, and is transferred to the transmission processing circuit 9.

(g) Based on the transmission type signal from the header processing circuit 8, the transmission processing circuit 9 selects either the information line from the delay circuit 4 or the information line from the transmission buffer 7 as an input path. As a result, the arriving bucket delayed by the delay circuit 4 or the packet transferred from the transmission buffer 7 is transferred to the multiplexing circuit 3 via the information line 1a. Furthermore, the transmission processing circuit 9 writes the new access control information transferred from the header processing circuit 8 in the access control information area of the sending packet. Note that the delay time in the delay circuit 4 corresponds to the time required for processing in the header processing circuit 8.

(H) The reception buffer 5 receives or discards the arriving packet transferred from the signal processing circuit 6 on the information line la based on the reception permission signal from the header processing circuit 8.

(S) When the above processes (c) to (g) are completed in (M/N) time for the arriving packet transferred on the information line la, the packet is transferred on the information line lb. Since the transfer of the arriving packet from the parallelization circuit 2 to the reception processing circuit 6 is started, the above-mentioned processes (c) to (g) for the arriving packet transferred on the information line 1b are started from this point.

(J) The above-described processing is sequentially performed on the packets transferred from the information line 1a to the information line In, and when the processing for the packets transferred on the information line ln is completed, the information is transferred as shown in FIG. &! Since the transfer of packets transferred on 1a begins, the processing for arriving packets that is sequentially performed in correspondence with the information line will continue to be performed from then on.

[Effects of the Invention] As explained above, according to the present invention, packets arriving at a communication node are parallelized by shifting the time required for header processing between transmission links, and the header processing is performed without being accumulated on a packet-by-packet basis. This reduces the packet processing delay at the communication node, and also allows the status of the communication node to be promptly notified to other communication nodes.
In addition to reducing packet transfer delay between terminals,
It is possible to efficiently perform state transitions in communication nodes.

[Brief explanation of drawings]

FIG. 1 is a communication node configuration diagram showing an embodiment of the present invention, FIG. 2 is a configuration diagram showing an example of a communication system to which the present invention is implemented, and FIG. 3 is a transfer used in the embodiment of the present invention. FIG. 4 is an explanatory diagram showing the transfer state of parallelized packets in an embodiment of the present invention. Explanation of symbols 1...Transmission link, 1a to 1n...Parallelized information lines, 2...Parallelization circuit, 2a to 2n...Parallelization FIFO corresponding to information line 13...Multiplexing circuit, 4...Delay circuit, 4a=4n...Delay circuit corresponding to parallelized information lines, 5...Receiving buffer, 5a to 5n...Receiving buffer corresponding to parallelized information lines, 6...・Receiving processing circuit, 7... Transmission buffer, ... Header processing circuit, 9.
. . . Transmission processing circuit, 10a to 10d . . . Communication node. Agent Patent Attorney Akio Namiki

Claims (1)

[Claims] 1) In each of a plurality of communication nodes connected to a ring-shaped or bus-shaped transmission link, a packet including a user information area, an address information area, and an access control information area is transferred on the transmission link. However, if the packet is addressed to its own node, it is processed so that it is received,
If a packet is to be forwarded to another node, it is processed to be relayed, and if there is space on the transmission link, the packet to be sent from the own node is processed to be transmitted on the transmission link. For each packet that comes,
In a packet processing method that is executed by referring to the address information and access control information, when the time required for transmission of one packet on a transmission path is M, the time required for processing per one packet at the communication node is M/ N (where N is a natural number), N packets that are serially transferred on the transmission link are processed in parallel with a delay of (M/N) time each, and processed continuously. A method of processing packets, characterized in that they are serialized back and sent out on a transmission link. 2) In each of a plurality of communication nodes connected to a ring-shaped or bus-shaped transmission link, a packet including a user information area, an address information area, and an access control information area is transferred on the transmission link. , if the packet is addressed to the own node, process it so that it is received,
If a packet is to be forwarded to another node, it is processed to be relayed, and if there is space on the transmission link, the packet to be sent from the own node is processed to be transmitted on the transmission link. For each packet that comes,
In the packet processing circuit that executes by referring to the address information and access control information, let M be the time required to transmit one packet on the transmission path, and let M/N be the time required to process one packet at the communication node. (where N is a natural number), a parallelization circuit that parallelizes and captures N packets serially transferred on the transmission link with a delay of (M/N) time, and N inputs and N outputs. , a delay circuit with N inputs and 1 output, a reception buffer with N inputs and 1 output, and N parallel packets taken in through the parallelization circuit are duplicated and transferred to the delay circuit with N inputs and N outputs and the reception buffer with N inputs and 1 output. a reception processing circuit for storing transmission packets from the own node in order to transmit them onto the transmission link when there is free space on the transmission link; a transmission processing circuit that selects and outputs any of the output packets from the transmission buffer; a multiplexing circuit that serializes the N parallel packets from the transmission processing circuit and outputs them onto the transmission link; and the reception processing circuit. Obtaining the address information and access control information of the received packet from the circuit, if determining that the packet should be received, instruct the reception buffer to that effect, and if determining that the packet should be transferred, instruct the transmission processing circuit to that effect. Furthermore, if it is determined that there is a transmission packet from the own node and that it can be transmitted on the transmission link, taking into account the presence or absence of a packet waiting to be transmitted in the transmission buffer, header processing instructs the transmission buffer and transmission processing circuit to that effect. A packet processing circuit comprising: a circuit;