JPH0496269A - Cmos semiconductor device - Google Patents

Abstract

PURPOSE:To prevent latching-up from being produced by lowering hfe of a lateral parasitic transistor by forming a second wall in an opposite polarity in a substrate between a first MOST and a second MOST to the depth or more of a first wall. CONSTITUTION:In a substrate 3 between a P-MOST 1 and an N-MOST 2 a stopper P well 20 is formed from the surface, deeper than a P well 6 by diffusion or ion implantation, on the surface side of which well 20 a P<+> contact region 21 is formed on which well 20 8 P<+> contact region 21 is formed on which region 21 an electrode is formed to apply voltage of a power supply VSS. AS s result, the effective base width of a parasitic lateral PNP transistor 11 is increased, permitting hfe thereof to sharply be reduced. Thus, even though the P well 6 is shallow and the hfe of the parasitic vertical NPN transistor 12 is higher, resistance to latching-up is greatly improved.

Description

[Detailed description of the invention] [Industrial application field]

The present invention provides CMO3 with effective latch-up countermeasures.
Related to semiconductor devices.

[Conventional technology]

FIG. 2 shows a circuit diagram of a CMOS inverter. 1 is P-MOST (enhancement type), 2 is N-
It is MO3T (enhancement type). Both MOST
The gates of I and 2 are commonly connected to form the input side, and the drains are commonly connected to form the output side. Then, the source of P-MOSTI is connected to the power supply VDD, and the source of P-MOSTI is connected to the power supply VDD.
The source of MOST2 is connected to power supply Vss. FIG. 3 is a cross-sectional view of this CMOS inverter constructed from one chip. On the P-MOSTl side, the N-type substrate 3 is used as it is, and a drain 4 and a source 5 are formed from the P' region so that a P channel is formed.
Regarding O3T2, a P well 6 is formed in the substrate 3, and a drain 7 and source 8 are formed from the N' region so that an N channel is formed. 9 is the N contact region for applying substrate bias of P-MOSTI, 10 is NMOST2
This is the P contact region for applying a P well bias.

[Problem to be solved by the invention]

By the way, in this configuration, a parasitic lateral PNP run risk 11 is formed in which the source 5 of the P-MOSTI is the emitter, the substrate 3 is the base, and the P well 6 is the collector.
In addition, the substrate 3 is the collector, the P well 6 is the base, and the N-MO
Parasitic vertical N with source 8 of ST2 as emitter
PN) run risk 12 is formed. A parasitic thyristor as shown in FIG. 4 is formed by these transistors 11 and 12. In other words, a single-chip CMOS inverter essentially has a built-in parasitic thyristor. 13 to 16 are resistors. As the miniaturization progresses, the base width (dl) of the lateral parasitic transistor 11 becomes smaller, and the base width (d2) of the vertical parasitic transistor 12 also becomes smaller. As a result, the hfe of both transistors 11 and 12 increases, the performance of the parasitic thyristor increases, and the parasitic thyristor easily operates using a noise current as a trigger, causing a current to flow from the power supply VDD to the power supply Vss. This current continues, which not only causes the CMOS inverter to malfunction, but also destroys the device. This is a serious failure called latch-up phenomenon. As mentioned above, this latch-up occurs when the transistor 11
．． The smaller the base widths d1 and d2 of the transistors 12, the more likely it is to occur. In particular, when the depth (depth d2) of the P-well 6 is less than 4 μm, the hfe of the vertical parasitic transistor 14 increases significantly, making the latch-up phenomenon extremely It is more likely to occur. The present invention solves these problems and provides a CMOS semiconductor device in which the hfe of the lateral parasitic transistor is lowered and latch-up is extremely unlikely to occur.

[Means to solve the problem]

To this end, the present invention provides a first MOST of a channel with a polarity opposite to that of the substrate, and a second MOST of a channel with the same polarity as the substrate formed in a first well with a polarity opposite to that of the substrate. In a CMOS semiconductor device in which a CMOS inverter is formed from a MOST, a second well is connected to the first MO3T and the second MO3T.
In the substrate between the ST and the depth of the first well,
It was constructed by forming the polarity opposite to the above.

[Effect]

In the present invention, the effective base width of the lateral parasitic transistor is increased due to the presence of the deeply formed second well, so that its hfe is significantly reduced and latch-up is less likely to occur.

【Example】

Examples of the present invention will be described below. FIG. 1 is a cross-sectional view of a CMOS inverter according to one embodiment. Here, the same components as in FIG. 3 are given the same reference numerals. In this embodiment, as shown in FIG.
A stopper P-well 20 (second well) is formed from the surface of the substrate 3 between the MOSTI and the N-MOST 2, deeper than the P-well 6 (first well) by diffusion or ion implantation. A P contact region 21 is formed on the side, and an electrode (not shown) for applying a voltage from a power supply SS is formed in this contact region 21. As a result, parasitic lateral PNP l-lan risk 11
Since the effective base width of is increased, its hre is significantly reduced. Therefore, even if the hfe of the parasitic vertical NPNt-transistor 12 in the shallow P-well 6 becomes high, the latch-up resistance is greatly improved. In particular, the depth of the P-well 6 is currently often less than 4 μm due to manufacturing processes and other reasons, but in such cases, it is effective to set the depth of the stopper P-well 20 to 4 μm or more. be. Further, since the voltage of the power supply Vss is applied to the contact region 21, that region functions as the collector of the lateral parasitic transistor 11, and the vertical parasitic transistor 12
will be largely bypassed. Note that the above-mentioned P-well 20 for the stopper is made of P-MOS.
It may be formed in a ring shape so as to surround T1. Moreover, when a P-type substrate is used contrary to the above embodiment, the lateral parasitic transistor becomes an NPN type and the vertical parasitic transistor becomes a PNP type, so in order to reduce the hfe of the lateral parasitic NPN l-run lister, A deep N-well for a stopper is formed. In this case, an electrode for applying the power supply VDD is formed in the N- contact region formed on the surface of the stopper N well. This electrode also functions as a bypass for the vertical parasitic transistor 12.

【Effect of the invention】

As described above, according to the present invention, the effective base width of the lateral parasitic transistor is increased by the deeply formed second well, and its hfe can be significantly reduced, so that a CMO3 circuit in which latch-up is unlikely to occur can be realized. There is an advantage.

[Brief explanation of drawings]

Fig. 1 is a cross-sectional view of a CMOS inverter circuit according to an embodiment of the present invention, Fig. 2 is a circuit diagram of a general CMOS inverter circuit, Fig. 3 is a cross-sectional view of a conventional CMOS inverter circuit, and Fig. 4 is a parasitic FIG. 2 is a circuit diagram of a thyristor. 1-P-MOST, 2-N-MOST, 3... N-type substrate, 4... Drain, 5... Source, 6-P well, 7... Drain, 8... Source, 9.10...
- Contact region for substrate bias, 11... Lateral parasitic PNP transistor, 12... Vertical parasitic N
PN transistor, 13-16...resistor, 20...
P well for stopper, 21... contact area. Agent Patent Attorney Tsuneaki Nagao Figure 1

Claims (3)

[Claims] (1), the first M of the channel of opposite polarity to that of the substrate;
OST and a second M of a channel of the same polarity as the substrate formed in the first well of opposite polarity to the substrate.
In a CMOS semiconductor device in which a CMOS inverter is formed from an OST, a second well is connected to the first MOS
A CMOS semiconductor device, characterized in that a CMOS semiconductor device is formed in a substrate between the T and the second MOST to a depth greater than the depth of the first well and having the opposite polarity. (2) The CMOS semiconductor device according to claim 1, wherein the first well has a depth of less than 4 μm, and the second well has a depth of 4 μm or more. (3) The CMOS semiconductor device according to claim 1 or 2, wherein an electrode for bypassing the vertical parasitic transistor is provided in the second well.