JPH0496573A - Signal processor - Google Patents

Abstract

PURPOSE:To improve the workability and the compatibility by providing a delay circuit adjusting a timing of A/D converter or the like and a monitor monitoring a picture synchronously with a delay picture element frequency signal to the processing unit, controlling a delay time while monitoring the picture and matching the timing to an optimum timing. CONSTITUTION:A pixel clock generating circuit 11 generates a pixel clock signal corresponding to a period of a vertical synchronizing signal VD and a horizontal synchronizing signal HD. Each delay circuit 12 gives a pixel clock signal delayed by 1nS each with a delay line 13 to a selector 14. An A/D converter 1 implements A/D conversion synchronously with the pixel clock signal delayed by 1nS. Then a digital color signal whose synchronization is delayed by 1nS is transmitted to the monitor system III. D/A conversion is implemented similarly in the monitor system III and a picture is displayed on a display device 24. Thus, the presence of picture disturbance is monitored and a selector 14 is switchingly driven by a controller 6 when any disturbance is in existence.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a signal processing device that performs synchronization adjustment of video signals of different standards, and in particular to a timing adjustment circuit suitable for use in devices such as color hard copy machines. It is related to.

[Conventional technology]

In CAD systems and the like, there is no standardization of video signals, and the reality is that pixel frequencies (pixel clock frequencies) differ depending on the type of host computer. For this reason, when an analog video signal with no data compatibility is supplied to a device that A/D converts an analog video signal, stores it in a storage means, and reproduces it, such as a color hard copy machine, the pixel frequency It is necessary to adjust the timing (synchronization) of A/D conversion according to the height of the signal.

Therefore, conventionally, the timing was first adjusted once for each color signal of R (red), G (green), and B (blue), then printed out, and the results were read and readjusted as necessary. .

[Problem to be solved by the invention]

However, it takes several minutes to adjust the timing and readjust it after checking the print results, so it takes several tens of minutes to make accurate timing adjustments for each signal, which makes the work inefficient. Ta.

The present invention has been made in view of the above-mentioned problems, and its object is to provide a signal processing device that can perform timing adjustment in real time while monitoring images of analog video signals of different standards.

[Means to solve the problem]

An object of the present invention is to provide a signal processing device that converts an analog video signal into a digital signal, stores the signal, and outputs the same to a hard copy device, including a signal generation circuit that generates a pixel frequency signal based on a synchronization signal of the analog video signal; A delay for selectively delaying the delay time of the pixel frequency signal, and supplying the delayed pixel frequency signal to an A/D converter, a latch circuit, etc. that controls signal transmission, and adjusting the timing of A/D conversion, etc. This is achieved by providing a circuit and a monitor device for monitoring an image synchronized with the delayed pixel frequency signal.

[Effect]

According to the signal processing device having the above configuration, the timing of conversion from an analog video signal to a digital signal and the timing of signal transmission by the latch circuit are controlled by the delayed pixel frequency signal, and the digital signal is D/A converted. The delay time can be controlled to match the optimal timing while monitoring the obtained image.

Therefore, color hard copy machines, etc. that use this signal processing device can synchronize in real time even when analog video signals of different standards are supplied, improving work efficiency and increasing compatibility. It is possible to improve the results.

〔Example〕

An embodiment of a timing adjustment circuit to which the present invention is applied will be described below with reference to the drawings. In this embodiment, a timing adjustment circuit is provided in a color hard copy that A/D converts an analog video signal, stores it, reads it out, and prints it out. Figure 1 shows the main points of a color hard printer. FIG. 3 illustrates a timing adjustment circuit.

First, the circuit configuration can be broadly divided into a video signal processing system I, a timing adjustment system (2), and a monitor system (2). The video signal processing system I and the timing adjustment system (2) are provided for each color signal R, G, and B, and in this embodiment, the color signal R will be illustrated and explained.

In the video signal processing system I, an A/D converter 1 is configured to A/D convert an analog video signal R into, for example, an 8-bit digital video signal. The latch circuit 2 controls data transfer, and the latch circuits 3a to 3d are provided to store digital video signals at predetermined addresses in the memory circuit 4. still,
The number of address circuits 3a to 3d installed is not limited to four,
It can be freely changed depending on the configuration of the memory circuit 4.

A data bus 5 reads video signals stored in the memory circuit 4 and transmits them to a print control system (not shown). The controller 6 is composed of a CPU, etc., and centrally controls data storage in the memory circuit 4, data readout onto the data bus 5, and timing adjustment system (2) to be described later.

The timing adjustment system ■ is the pixel clock generation circuit 11
, for example, is composed of six delay circuits 12. The pixel clock generation circuit 11 converts the pixel frequency signal (pixel clock signal) in the present invention into a horizontal synchronization signal HD,
It is generated in response to the vertical synchronization signal VD. Therefore, even if the video signal is not standardized like an NTSC television signal, a pixel clock signal corresponding to the synchronization signal of the supplied video signal can be obtained.

The delay circuit 12 includes ten delay lines 13 and a selector 14 that delay each pixel crotter signal in ten stages, for example, every 1 nanosecond (hereinafter, the unit is expressed as nS). The delay time is selected by the controller 6, and the delayed pixel clock signal corresponds to the delayed pixel frequency signal in the present invention. Note that the number of delay circuits 12 is provided corresponding to the number of A/D converters, latch circuits, etc., and is not limited to the six illustrated.

The monitor system ■ is provided to monitor images when performing synchronization adjustment, and includes four latch circuits 21.
a to 21d, a latch circuit 22, a D/A converter 23, and a display device 24.

Next, the circuit operation will be explained.

The analog video signal R for one frame is sequentially supplied to an A/D converter 1, which converts it into an 8-bit digital color signal and supplies it to a latch circuit 2. The latch circuit 2 transmits the digital color signal to each latch circuit 3 at predetermined intervals.
a to 3d, and each latch circuit 3a to 3d operates to divide the digital color signal and store it in each address of the memory circuit 4.

At this time, the timing adjustment system (2) operates as described below, and while monitoring the image, in other words, performs image synchronization adjustment in real time.

That is, the pixel crotter generation circuit 11 generates a pixel crotter signal corresponding to the cycles of the vertical synchronizing signal VD and the horizontal synchronizing signal HD. The pixel clock signal is supplied to six delay circuits 12.

Each delay circuit 12 supplies a pixel clock signal delayed by lnS by the play line 13 to the selector 14.

If the play line 13 closest to the player is a line with a delay of 1 nS, and if the selector 14 selects the leftmost play line 13 using the controller 6, then the delay will be 1 nS.
The delayed pixel clock signal is sent to the video signal processing system I.
An A/D converter 1, a latch circuit 2, latch circuits 3a to 3d, and a latch circuit 21 forming a monitor system.
a to 21d, the latch circuit 22, and the D/A converter 23.

As a result, the A/D converter 1 performs A/D conversion in synchronization with the pixel clock signal delayed by 1 nS, and each of the latch circuits 2.3a to 3d also performs a latch operation. Then, the digital color signal whose synchronization is delayed by 1 ns is used as a monitor system.
transmitted to. Also in monitor system ■, latch operation and D/A synchronized with pixel clock signal delayed by 1 ns.
Conversion is performed, and an image based on the analog video signal is displayed on the display device 24.

At this time, if the timing is not correct, the displayed image will be distorted, and if the timing is correct, there will be no image disturbance.

Therefore, the presence or absence of image disturbance is monitored, and if there is any disturbance, the selector 14 is switched and driven by the controller 6 while monitoring the disturbance. Then, the play line 13 without any disturbance is selected, in other words, the delay time of the pixel crotter signal is selected, and the selection operation is stopped when the disturbance disappears.

At this point, the image monitor is no longer needed, so the drive of the monitor system is stopped. Further, the synchronized digital color signal is stored in the memory circuit 4.

In this manner, by controlling the delay of the pixel crotter signal, a digital color signal without disturbance can be obtained. Then, by reading out the stored digital color signal from the memory circuit and printing it, it is possible to print an image in which the timing has been adjusted. Therefore, the troublesome effort of adjusting the timing while checking the print result is unnecessary.

Next, another example of the delay circuit I2 will be explained with reference to FIG.

In the embodiment described above, switching of the selector 14 was performed by the controller 6. However, the selector 14 may have a structure in which a dip switch 15 is provided as shown in FIG. According to this configuration, the optimum play line 13 can be selected by manually operating the dip switch 15 and switching the selector 14 while viewing the monitor image as described above.

Although the present invention has been described in detail above, the present invention is not limited to the above, and various modifications are possible.

Furthermore, the drive and drive stop of the monitor system (2) may be controlled by any one of digital signal supply and cutoff control, power supply and cutoff control, and the like.

[Effects of the Invention] As described above, the signal processing device according to the present invention performs A/I conversion and signal processing while performing real-time image monitoring in response to the synchronization signal of the supplied analog video signal. The timing of transmission can be controlled.

Therefore, even if an analog video signal of a different standard is supplied to a device that hard copies images based on analog video signals, timing adjustment can be easily performed and the workability of timing adjustment can be improved.

[Brief explanation of drawings]

Figure 1 shows a complete system to which the present invention is applied! FIG. 2 is a circuit diagram showing one embodiment of the processing circuit. FIG. 2 is a circuit diagram showing another configuration of the delay circuit. Symbols in the figure: 1; A/D converter, 2.3a to 3d, 21a to 21d, 22; latch circuit, 4; memory circuit, 11; pixel clock generation circuit, ; delay circuit, ; play line, :Selector, :D/A converter, :Display device, video signal processing system, timing adjustment system, monitor system.

Claims (1)

[Claims] A signal processing device that converts an analog video signal into a digital signal, stores it in a storage means, and outputs it to a hard copy device, the signal processing device generating a pixel frequency signal based on a synchronization signal of the analog video signal, The timing of converting the analog video signal to a digital signal is controlled by the delayed pixel frequency signal obtained by delaying the pixel frequency signal by a desired time, and the delayed pixel frequency signal is controlled while monitoring an image based on the digital signal. A signal processing device configured to control delay.