JPH0497281A - Display control circuit - Google Patents

Abstract

PURPOSE:To improve display quality by generating a 2nd inversion signal having higher frequency than a 1st inputted inversion signal by a column direction driving means and selecting either the 1st inversion signal or the 2nd inversion signal. CONSTITUTION:The column direction driving means 1 scans a row direction electrode along a column direction and outputs a display signal and the scanning signal of a column direction electrode to a row direction driving means 17. The control means 12 is connected to the means 1 so as to output the display signal, the scanning signal and the 1st inversion signal. Then, the means 1 generates the 2nd inversion signal having higher frequency than the 1st inputted inversion signal, and a signal selection means selects either the 1st inversion signal or the 2nd inversion signal; for example, when many display spots exist on the column direction electrode, the 2nd inversion signal is selected. Thus, undesired display in a non-display area on the column direction electrode where comparatively many display spots exist is prevented and the display quality is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a display control circuit for realizing a display operation on, for example, a simple matrix type liquid crystal display element.

2. Description of the Related Art In a simple matrix type liquid crystal display element, a plurality of row direction electrodes and a plurality of column direction electrodes are formed on a pair of transparent substrates so as to be perpendicular to each other. Each row direction electrode is scanned along the column direction by a column direction drive circuit, the column direction electrode is scanned along the row direction by a row direction drive circuit, and a display signal is output for each column direction electrode. The row-direction drive circuit and column-direction drive circuit operate as described above, respectively, based on display signals and scanning signals from the CPTJ (central processing circuit).

In order to prevent a DC voltage from being applied to the liquid crystal interposed between the row direction electrode and the column direction electrode, the self-display signal is added to a polarity inversion signal whose polarity is periodically inverted in the CPU, The voltage is applied to the liquid crystal in a state where it is converted into an alternating current and the polarity is periodically reversed.

An example of such a polarity inversion signal FRM is shown in FIG. 8(2), and FIG. 8(1) is a clock signal generated within the CPU. For example, the polarity inversion signal FRM corresponds to the operational duty (for example, 1/
It is generated by counting the number of clocks corresponding to 146 duty) and switching the polarity by a toggle operation. That is, the clock signal LCK shown in FIG. 8(1) is counted by a counter in the CPU, and the clock signal LC
The polarity inversion signal FR is generated at the first falling edge of K.
M switches from low level to high level.

Below, 146 clock signals LCK are counted, and 14
At the falling timing of the sixth clock signal LCK, the polarity inversion signal FRM switches from high level to low level. Thereafter, the polarity inversion signal FRM is similarly generated by performing a toggle operation.

Problems to be Solved by the Invention In the conventional liquid crystal display device using the above-mentioned polarity inversion signal FRM, as shown in the display example of FIG. In the case of a column direction electrode with many addresses lit in the Y direction in FIG. 7, the lit display area 6
Regarding No. 1, on the column direction electrode on the downstream side in the Y direction, the sixth
It is known that an erroneous display 62 indicated by a broken line in the figure occurs.

Such erroneous display 62 significantly deteriorates the display quality of the liquid crystal display device 11.

An object of the present invention is to solve the above-mentioned technical problems and provide a display control circuit with significantly improved display quality.

Means for Solving the Problems The present invention provides a plurality of row direction electrodes and column direction electrodes formed on a pair of transparent substrates and connected to display means for displaying,
a row direction driving means for scanning the column direction electrodes along the row direction and outputting a display signal; and a row direction drive means connected to the display means and the row direction driving means, for scanning the row direction electrodes of the display means along the column direction and A column-direction drive means that outputs a display signal and a scanning signal for column-direction electrodes to the row-direction drive means; the column direction driving means includes a signal generating means for generating a second polarity inversion signal having a higher frequency than the input first polarity inversion signal; A display control circuit characterized by comprising a signal selection means for selecting either one of the signal and the second polarity inversion signal.

According to the present invention, when displaying on the display means, the row direction drive means scans the column direction electrodes along the row direction.The column direction drive means scans the row direction electrodes along the column direction. , outputs a display signal and a scanning signal for column direction electrodes to the row direction driving means. A control means is connected to this column direction driving means, and outputs a display signal, a scanning signal, and a first polarity inversion signal. The first polarity reversal signal is used to periodically switch the polarity of the display signal applied to the display means to avoid a situation where a DC voltage is applied to the display means.

In the column direction driving means, the signal generating means generates a second polarity inversion signal having a higher frequency than the input first polarity inversion signal, and the signal selection means selects either the first polarity inversion signal or the second polarity inversion signal. chooses one.

Therefore, in the present invention, when there are many display locations on the column direction electrodes, the second polarity inversion signal is selected. Thereby, it is possible to prevent an undesired display from being realized in the non-display area on the column direction electrode where there are relatively many display areas, and the display quality can be significantly improved. Further, since either one of the first and second polarity inversion signals is selected, when there are relatively few display areas on the column direction electrodes, it is possible to use the first polarity inversion signal to reduce power consumption. can.

Embodiment FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a block diagram of a data processing device 2 in which the common drive circuit 1 is used, and FIG. 3 is a block diagram of a data processing device 2 in which the common drive circuit 1 is used. 2
FIG. This data processing device 2 is so-called a notebook size, and a first operating section 3 and a second operating section 4 are configured to be openable and closable at a connecting section 5. The second operation section 4 includes a cursor key 6, a function setting key 7, a character entry key 8, a number entry key 9, and the like. On the other hand, so-called transparent touch keys 10 and a liquid crystal display device 11 are arranged in the first operation section 3 .

Such a data processing device 2 includes, for example, a CPU (central processing circuit) including a microprocessor, etc.
12, and the transparent touch key 10 is connected to the CPU 12.
and a RAM (Random Access Memory) 13 to which each key manual means of the second operation unit 4 is connected, and which is used as a storage area for various input data and a working area for data during operation, and a program that defines control operations of the CPU 12. A ROM (read only memory) 14 in which font data, display font data, calendar data, etc. are stored is connected.

Furthermore, the CPU 12 includes a clock circuit 15 for timekeeping, a common drive circuit 1 that controls the display operation of the liquid crystal display device 11 as will be described later, and a common drive circuit 1 based on a contrast signal from the common drive circuit 1. A liquid crystal power supply circuit 16 that changes the liquid crystal power supply potential to be supplied and is switched between an operating state B and a stopped state by a control signal from the CPU 12.
are connected. A plurality of (eight in this embodiment) segment drive circuits 17 are connected to the common drive circuit 1,
Together with the common drive circuit 1, it controls the display state of the liquid crystal display device 11. The liquid crystal display device 11 includes a pair of transparent substrates 11a.
, llb, a common electrode 11c and a segment electrode 11d are formed, with a liquid crystal layer 11e interposed therebetween.

A block diagram of the common drive circuit 1 is shown in FIG. The common drive circuit 1 is supplied with a write/read control signal R/W, a clock signal φ, a busy signal BY, a chip enable signal CE, etc. from the CPU 12, and also has a control circuit 19 supplied with address data AD, display data DI, etc. Equipped with Of these, the display data DI is input via the buffer 20. Further, the common drive circuit 1 outputs a frame signal PR, a control signal DIS for controlling ○N10FF displayed by the segment electrodes, and a clock signal LCK to the segment drive circuit 17. As described above, such a data processing device 2 is a notebook-sized portable device, and various reference voltages necessary for the operation of the data processing device 2 are generated from a power supply circuit 26 connected to a battery 25.

A data processing circuit 21 is connected to the control circuit 19, and the CP
Logical operations (SET, AND, OR,
After performing OR, etc.), the data is sent to the segment drive circuit 17. The memory control circuit 22 sends the address data sent from the CPU 12 to which segment drive circuit 17.
A relative address in one of the selected segment drive circuits 17 is generated.

The timing generation circuit 23 generates clock signals and the like used for various calculation processes in the common drive circuit 1.
A reference clock signal from an oscillator 24 is provided.

The common signal control circuit 27 and the common side decoder 28 use the clock signal generated by the timing generation circuit 23 to generate a common signal to be supplied to the common electrode of the liquid crystal display device 11. Further, two window processing circuits having the configuration and operation described below are connected to the control circuit 19, the contrast adjustment circuit 46 stores the density displayed on the liquid crystal display device 11, and the density data is sent to the CPU 12.
It is set from Contrast adjustment of the liquid crystal display device 11 is performed by the liquid crystal power supply circuit 16 shown in FIG. 2 based on density data in the contrast adjustment circuit 46, and the liquid crystal power supply potential from the liquid crystal power supply circuit 16 is taken into the common drive circuit 1 A liquid crystal voltage input section 17 is provided for this purpose.

FIG. 4 is a block diagram showing the configuration of a signal generation circuit 63 according to an embodiment of the present invention provided in the common drive circuit 1. The signal generation circuit 63 is, for example, an 8-bit FRM.
A register 64 is provided, and FRM data is input from the CPL 112 through software processing and stored therein. F.R.M.
The lower seven bits of the register 64 determine the period of a second polarity inversion signal FRM2, which will be described later. The most significant bit FX is C
A first polarity reversal borrow sign FRMI input from the PU12,
It defines the selection operation of the signal selection circuit 65 which selects either one of the second polarity inversion signal FRM2 which is generated as described later and has a higher frequency than the first polarity inversion signal FRMI.

The lower 7 bits of FRM data from the FRM register 64 are stored in the FRM data storage section 66.

On the other hand, the signal generation circuit 63 includes a count circuit 67 that performs a +1 increment operation every time the clock signal LCK is input, and the count value is compared with the FRM data in a comparison circuit 68. While the comparator circuit 68 is detecting a mismatch between the input data, a high-level mismatch detection signal, for example, is input to the counting circuit 67 via the line 11, and the incrementing operation is continued.

When the comparison circuit 68 detects a matching state between input data,
A match signal falling from high level to low level is output to line 12, and this match signal is input to the count circuit 67 to reset the counting operation. Further, the coincidence signal is input to six binary counters, and the least significant bits of the six binary counters are input to an AND circuit 70 forming the signal selection circuit 65.

The most significant bit FX of the FRM register 64 is input to the AND circuit 70, and the inverted signal of the most significant bit FX by the inverting circuit 71 is input to the AND circuit 72,
The first polarity inversion signal FRMI is input together with the first polarity inversion signal FRMI. The outputs of the AND circuits 70 and 72 are input to the OR circuit 73, and the output of the OR circuit 73 becomes the output of the signal selection circuit 65, which outputs the second polarity inversion signal FRM2, which is the output of the binary counter 69, and the first polarity inversion signal. Outputs either FRMI or FRMI.

FIG. 5 is a block diagram showing a circuit example of the signal generation circuit 63. The FRM register 64 and the FRM data storage section 66 are provided with a latch circuit 74 that stores 8-bit data from the CPU 12, and the lower-order data Do to D6 on the output side are stored in the six exclusive bits included in the comparison circuit 68. The outputs of each exclusive OR circuit 75 are input in common to a NAND circuit 76, and the output thereof is input to the binary counter 69.

The count circuit 67 includes a 7-bit latch circuit 77 that latches and outputs input data every time the clock signal LCK is input.
8, and each time the output data from the latch circuit 77 is input, the increment circuit 78 increases the input data by +1.
Increments and outputs 7 bits in parallel. The way it comes out is the inversion circuit 79 and NOR circuit 8 provided for each bit.
Each bit is input to the latch circuit 77 via the respective bits. The seven NOR circuits 8o include the NA
The outputs of the NDAND circuits are inverted by an inverting circuit 81,
It is input as a reset signal for the count circuit 67.

The output of the 7-bit latch circuit 77 is sent to a comparison circuit 68.
are respectively input to seven exclusive OR circuits 75 configuring. 'That is, when the 7-bit parallel output of the latch circuit 77 and the 7-bit parallel output of the latch circuit 74 all match bit by bit, the NAND circuit 7
All 7-bit inputs of NAND circuit 76 become logic "1", and only at this time, the output of NAND circuit 76 switches from high level to low level, and six binary counters count up at this timing. Also, the NAND circuit 76
The signal switching from high level to low level from
All outputs of the seven OR circuits 80 of the count circuit 67 are fixed at low level, and the latch circuit #@77 is reset. The OR circuit 73 shown in FIG. 4 of the signal selection circuit 65 is
It is composed of a NOR circuit 82 and an inversion circuit 83.

When the most significant bit D7 of the latch circuit 74 is "1", the AND circuit 70 is conductive and the AND circuit 71 is cut off. Therefore, the OR circuit 73 converts the second polarity inversion signal FRM2 from the binary counter 69 into polarity inversion signals PR, M
Output as . On the other hand, when the most significant bit D7 of the latch circuit 74 is "0", the AND circuit 72 becomes conductive and the AND circuit 70 is cut off. In this case, the first polarity inversion signal FR from the CPU 12 input to the AND circuit 72
MI is output from the signal selection circuit 65 as a polarity inverted signal FRM.

FIG. 6 is a time chart explaining the operation of this embodiment. A case will be described in which FRM data N is set in advance from the CPU 12 to the lower seven bits of the FRM register 64 shown in FIG. At the falling timing of the clock signal LCK that is first input after the count circuit 67 is reset, the count circuit 67 outputs the count value -1, and the comparison circuit 68 outputs the discrepancy signal, and the count of the count circuit 67 is Continue the operation.

At this time, the output of the comparison circuit 68 is "1", and the FR
If the most significant bit of the M register 64 is "1", the high level output of the binary counter 69 is the polarity inversion signal F.
The signal is output as RM, and the waveform shown in FIG. 6(2) is obtained.

After this, when the count value of the count circuit 67 becomes -N,
The outputs of the seven exclusive OR circuits 75 included in the comparison circuit 68 all become logic "1", and at the switching timing when the output of the NAND circuit 76 switches from high level to low level, the non-inverting outputs of the six binary counters go low. The level is switched to obtain the waveform shown in FIG. 6(2).

Thereafter, by repeating the same operation, the second polarity inversion signal FRM2 from the six binary counters is outputted as the polarity inversion signal FRM.

Such a polarity inversion signal FRM has a higher frequency than the first polarity inversion signal FRMI input from the CPU 12.

Therefore, as shown in the display example of the liquid crystal display device 11 in FIG.
This will prevent the situation from occurring.

On the other hand, in the display area 59 of the liquid crystal display device 11, for segment electrodes with relatively few lighting locations, the most significant bit of the FRM register 64 is set to "0", and the CPU 12
The first polarity reversal borrow sign FRMI from FRMI is used. As a result, the first polarity inversion signal FR is output from the signal generation circuit 63 shown in FIG.
It can be configured to output MI. Thereby, for example, the power consumption of the data processing device 2 can be reduced.

Effects of the Invention According to the present invention, in the column direction driving means, the signal generating means generates a second polarity inversion signal having a higher frequency than the input first polarity inversion signal, and the signal selection means generates a second polarity inversion signal having a higher frequency than the input first polarity inversion signal. Either one of the first polarity inversion signal and the second polarity inversion signal is selected. Therefore, in the present invention, when there are many display locations on the column direction electrodes, the second polarity inversion signal is selected. Thereby, it is possible to prevent an undesired display from being realized in the non-display area on the column direction electrode where there are relatively many display areas, and the display quality can be significantly improved. Also, since either one of the first and second polarity inversion signals is selected,
If there are relatively few display areas on the column direction electrodes, the first
Power consumption can be reduced by using the polarity inversion signal.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a common drive circuit 1 according to an embodiment of the present invention, FIG. 2 is a block diagram of a data processing device 2, FIG. 3 is a plan view of the data processing device 2, and FIG. 4 is a block diagram of a common drive circuit 1 according to an embodiment of the present invention. FIG. 5 is a block diagram showing a circuit example of the signal generating circuit 63, FIG. 6 is a time chart explaining the operation of this embodiment, and FIG. 7 is a block diagram of the signal generating circuit 63 of this embodiment. FIG. 8 is a time chart of the conventional example. 1... Common drive circuit, 2... Data processing device, 1
DESCRIPTION OF SYMBOLS 1... Liquid crystal display device, 17... Segment drive circuit, 63... Signal generation circuit, 64... FRM register, 65... Signal selection circuit, 66... FRM data storage part, 67... ...Count circuit, 68...Comparison circuit,
69...Binary Counter Agent Patent Attorney Stroke Count Keiichi Part Figure Figure Procedure Amendment (Method) December 4, 1990 Figure Figure Patent Application Hei 2-213164 2. Name display control circuit 3 of the invention; Relationship with the case of the person making the amendment Applicant Address 22-22 Nagaike-cho, Abeno-ku, Osaka Name (50
4) Sharp Corporation Representative: Haruo Tsuji 4, Agent address: 1-13-38 Nishihonmachi, Nishi-ku, Osaka Shinko Sangyo Building Country Equipment EX 0525-5985 INTAPT
International FAX (06) 538-0247 (representative) 6, Drawings subject to amendment 7, Contents of amendment: Engraving of drawings (no change in content)

Claims (1)

[Claims] A plurality of row direction electrodes and column direction electrodes are formed on a pair of transparent substrates and are connected to a display means for displaying, and the column direction electrodes are scanned along the row direction and display signals are transmitted. A row direction drive means for outputting a display signal and a scanning signal for the column direction electrodes to the row direction drive means. column-direction driving means that outputs a display signal, a scanning signal,
and a control means for outputting a first polarity inversion signal for periodically switching the polarity of the display signal applied to the display means, and the column direction driving means has a higher frequency than the input first polarity inversion signal. A display control circuit comprising: signal generating means for generating a second polarity inversion signal; and signal selection means for selecting either the first polarity inversion signal or the second polarity inversion signal.