JPH0497530A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH0497530A
JPH0497530A JP2215358A JP21535890A JPH0497530A JP H0497530 A JPH0497530 A JP H0497530A JP 2215358 A JP2215358 A JP 2215358A JP 21535890 A JP21535890 A JP 21535890A JP H0497530 A JPH0497530 A JP H0497530A
Authority
JP
Japan
Prior art keywords
film
substrate
contact hole
semiconductor substrate
melted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2215358A
Other languages
Japanese (ja)
Inventor
Masahiro Nakatani
昌弘 中谷
Akihiro Kanda
神田 彰弘
Takehiro Hirai
健裕 平井
Mitsuo Tanaka
光男 田中
Isao Miyanaga
績 宮永
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2215358A priority Critical patent/JPH0497530A/en
Publication of JPH0497530A publication Critical patent/JPH0497530A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To make step coverage of Al better and prevent disconnection of Al in a contact hole portion where the aspect ratio is high because melted Al directly flows into the contact hole by applying melted Al onto a semiconductor substrate. CONSTITUTION:After a diffusion layer 2 is formed on an Si substrate 1, an S1O2 film 3 is formed on the substrate 1. Next, the S1O2 film 3 is dry etched with, for example, resist as a mask, in order to form a contact hole 4. While the substrate 1 is kept heated to an appropriate temperature below 500 deg.C, a melted Al film 6 is applied onto the surface of the substrate 1 by dropping melted Al of approximately 700 deg.C through a nozzle 11 onto the rotating Si substrate 1. At this time, even if the surface of the film 6 is not flat, it can be made flat by etching. The coverage of Al, in particular, in the step-difference portion, is improved considerably. The disconnection of Al can be prevented, improving the reliability of devices.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は半導体集積回路装置の製造方法に関するもので
あa 従来の技術 半導体基板上の金属配線材料としてAl膜が使われてお
り、近鍛 そのAl膜を形成する限 スパッタ蒸着が用
いられることが主流となっていも第4図はこの従来のス
パッタ蒸着法により製造した半導体装置の断面図であ&
Si基板1に拡散層2を形成した黴 Si基板1上にS
10を膜3を形成し それを例えばレジストをマスクに
してドライエツチングすることによりコンタクトホール
4を形成した丸 スパッタ蒸着でAl膜6を形成すも 
このように構成された従来の方法においては 図の段差
部でのA1のステップカバレッジの小さいことが大きな
問題になっていも スバ・ツタ蒸着の中で&  Al−
8j−Cu、Al−8i等のAj合金IL  MO,W
、  Ta等の高融点金属膜およびM o S i *
、WSig等のシリサイド膜の形成に(よ 上記問題点
を少しでも軽減するがために次に述べる高速スパッタ法
が用いられも これ(瓜 スパッタされた原子または分
子が高いエネルギーを持っているた樵 基板をあたため
なくても付着強度の強い金属膜を形成できること、また
10−”Torrから10−”To r r程度の低真
空中で膜を形成するため蒸着金属の”まわり込み′”が
よくなり、ウェハ段差部のステップカバレッジの良いこ
と、またスパッタ効率も通常スパッタ法に比べて高いこ
とが特徴であム 発明が解決しようとする課題 しかしなか収 今也 より一層コンタクトホールの微細
化が進収 アスペクト比が大きくなるに伴((高速スパ
ッタ法のような従来の製造方法においてもコンタクトホ
ール部分におけるA1のステップカバレッジが悪くなり
、より微細な構造を有するデバイスを作成する時にAl
の断線等が大きな問題となム 本発明はかかる点に鑑へ 半導体基板上に溶融したAl
を塗布することによりA1配線の断線のない製造方法を
提供することを目的とすム課題を解決するための手段 本発明ζよ 上記課題を解決するためJQ  半導体の
一主表面上に絶縁膜を形成した微 前記絶縁膜を選択的
に除去してコンタクトホールを形成し前記半導体表面に
溶融したAlを塗布L  Alをコンタクトホール部に
充填するものであム作用 本発明の作用番よ 以下の通りであム 溶融したAlが直接にコンタクトホールに流れ込むため
に アスペクト比の大きいコンタクトホール部において
k  Alのステップカバレッジが良くなり、Alの断
線を防ぐことができも実施例 以下、本発明の実施例について第1図〜第4図を参照し
ながら説明すも (実施例1) 第1図A−Cは本発明の第1の実施例を示す製造工程断
面図であム 第1図Aにおいて、まずSi基板1に拡散層2を形成し
た喪 Si基板1上にS + 0 * II! 3を形
成すも 次ζミ 例えばレジストをマスクにして5IO
a膜3をドライエツチングしてコンタクトホール4を形
成すも そして、第1図Bのように Si基板1を50
0℃以下の適温に加熱させたまま、 700℃程度に溶
融したA15をノズル11より回転したSi基板l上に
滴下することにより、81基板1表面に溶融したAll
!:6を塗布すム このK  AlH3に凹凸が生じて
もエツチングにより平坦にすることができも 第1図C
は以上の工程によるコンタクトホール部分での断面図で
、特に段差部でのA1のカバレッジが従来の第4図の例
の場合と比べて大幅に改善さh  Alの断線を防ぐこ
とができ、デバイスの信頼性の向上にっなが(実施例2
) 第2図A−Cは本発明の第2の実施例を示す製造工程断
面図であム 第2図Aにおいて、まず81基板1に拡散層2を形成し
たa Si基板l上にS + O*膜3を形成しそして
例えばレジストをマスクにして5101膜3をドライエ
ツチングしてコンタクトホール4を形成すも 次に S
i基板1表面にA1より高い融点を有する所望の厚さの
金属膜7を表面全体に形成すも その後例えt′L S
i基板1を500℃以下の適温に加熱させたまま、 7
00℃程度に溶融したAl5をノズル11より回転した
Si基板1上に滴下することにより、Si基板1表面に
A1膜6を塗布すム この時、Al膜6に凹凸が生じて
もエツチングにより平坦にすることができ4次番ミ  
例えばレジストをマスクにしてAlIO2ドライエツチ
ングして配線パターンを形成すもこの実施例によれ・ば
 金属−金属同士の親和性のためGQ、Si基板1とA
lIO2付着より、高融点金属膜7とAl膜6の方が付
着しやすくなり、第2図Bのようにコンタクトホール部
でのAlのカバレッジが上記第1の実施例よりさらに良
くなり、A1の断線が大幅に改善されも な耘 第2図Cのよう置 上記の工程の中で、高融点金
属膜7を形成する前に予め所望の厚さのシリサイドM8
を形成してもよ賎 熱処理に伴う高融点金属膜7とSi
基板1との直接の反応がこのシリサイド膜8により抑制
され コンタクト抵抗値は低くなム また この時のシ
リサイド膜8と高融点金属膜7の形成には高速スパッタ
法のような蒸着法を用いてもよu% (実施例3) 第3図C−Cは本発明の第3の実施例を示す製造工程断
面図であム 第3図Aにおいて、まずSi基板lに拡散層2を形成し
た抵 Sl基板1上に5102膜3を形成し例えばレジ
ストをマスクにして5102膜3をドライエツチングし
てコンタクトホール4を形成する。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for manufacturing a semiconductor integrated circuit device.a.Prior Art An Al film is used as a metal wiring material on a semiconductor substrate. Although sputter deposition has become the mainstream method for forming films, Figure 4 is a cross-sectional view of a semiconductor device manufactured by this conventional sputter deposition method.
Mold with diffusion layer 2 formed on Si substrate 1 S mold formed on Si substrate 1
A contact hole 4 is formed by forming a film 3 on 10 and dry etching it using, for example, a resist as a mask.Also, an Al film 6 is formed by sputter deposition.
In the conventional method configured in this way, even though the small step coverage of A1 at the step part shown in the figure is a big problem, it is difficult to obtain &Al-
Aj alloy IL MO, W such as 8j-Cu, Al-8i
, a high melting point metal film such as Ta, and M o Si *
To form silicide films such as WSig, the following high-speed sputtering method is used to alleviate the above problems. It is possible to form a metal film with strong adhesion strength without heating the substrate, and because the film is formed in a low vacuum of about 10-” Torr to 10-” Torr, the “wrapping” of the deposited metal is improved. However, the problems that the present invention aims to solve have been resolved by the present invention, which is characterized by good step coverage of the wafer step part and higher sputtering efficiency than normal sputtering methods. As the aspect ratio increases ((Even in conventional manufacturing methods such as high-speed sputtering, the step coverage of A1 in the contact hole portion becomes worse, and when creating devices with finer structures, Al
In view of this problem, the present invention has been designed to solve the problem of wire breakage, etc.
The purpose of the present invention is to provide a manufacturing method that does not cause disconnection of A1 wiring by coating JQ. The formed insulating film is selectively removed to form a contact hole, and molten Al is applied to the semiconductor surface to fill the contact hole portion.The action of the present invention is as follows. Since the molten Al flows directly into the contact hole, the step coverage of k Al is improved in the contact hole portion with a large aspect ratio, and disconnection of Al can be prevented. will be explained with reference to FIGS. 1 to 4 (Embodiment 1) FIGS. 1A to 1C are manufacturing process cross-sectional views showing the first embodiment of the present invention. First, a diffusion layer 2 is formed on a Si substrate 1.S+0*II! 3 is formed, but the next
The contact hole 4 is formed by dry etching the a film 3, and then, as shown in FIG.
By dropping A15 molten to about 700°C from the nozzle 11 onto the rotated Si substrate 1 while heating it to an appropriate temperature below 0°C, the molten Al is deposited on the surface of the 81 substrate 1.
! :Apply 6. Even if unevenness occurs on AlH3, it can be made flat by etching.
Figure 4 is a cross-sectional view of the contact hole portion created by the above process, and shows that the coverage of A1, especially at the stepped portion, has been greatly improved compared to the conventional example shown in Figure 4. Improving the reliability of (Example 2)
) FIGS. 2A to 2C are cross-sectional views showing the manufacturing process of a second embodiment of the present invention. In FIG. 2A, first, a diffusion layer 2 is formed on an 81 substrate 1. The O* film 3 is formed, and the 5101 film 3 is dry-etched using, for example, a resist as a mask to form a contact hole 4. Next, S
A metal film 7 of a desired thickness having a melting point higher than A1 is formed on the entire surface of the i-substrate 1, but then, for example, t'L S
While heating the i-board 1 to an appropriate temperature of 500°C or less, 7
By dropping Al5 melted at about 00°C onto the rotated Si substrate 1 from the nozzle 11, the A1 film 6 is applied to the surface of the Si substrate 1. At this time, even if the Al film 6 has unevenness, it is flattened by etching. can be 4th number mi
For example, according to this embodiment, a wiring pattern is formed by dry etching AlIO2 using a resist as a mask.
The high melting point metal film 7 and the Al film 6 adhere more easily than the lIO2 adhesion, and as shown in FIG. In the above process, before forming the high melting point metal film 7, the silicide M8 of the desired thickness is
The high melting point metal film 7 and Si may be formed during heat treatment.
Direct reaction with the substrate 1 is suppressed by this silicide film 8, resulting in a low contact resistance value.Also, the silicide film 8 and the high melting point metal film 7 are formed using a vapor deposition method such as a high-speed sputtering method. (Example 3) Figure 3C-C is a cross-sectional view of the manufacturing process showing the third example of the present invention.In Figure 3A, first, a diffusion layer 2 was formed on a Si substrate 1. A 5102 film 3 is formed on a resistive Sl substrate 1, and a contact hole 4 is formed by dry etching the 5102 film 3 using, for example, a resist as a mask.

さらにその上に下層配線膜としてA1よりも高い融点を
有する金属膜7を形成すも 高融点金属膜7の形成には
スパッタ蒸着法を用いてもよ1%、  次善′、第3図
Bのよう番ミ  高融点金属7を下層配線膜とし この
上に層間絶縁膜9を約800 nm形成し これを例え
ばレジストをマスクにしてドライエツチングすることに
よりコンタクトホールを形成し 下層配線膜を露出させ
も 次へ 再びAlよりも高い融点を有する金属膜7を
層間絶縁膜9上に形成し これを例えばレジストをマス
クにしてドライエツチングすることにより配線パターン
を形成すム その&Si基板1を500℃以下の適温に
加熱させたまま、 700℃程度に溶融したA15をノ
ズル11より回転したSi基板1上に滴下する方法を用
いて、上層配線膜となる溶融したAl膜6を塗布するこ
とにより、層間絶縁膜9のコンタクトホール部にAlを
充填させも第3図C+−層間絶縁膜9のコンタクトホー
ル部において、上層配線膜としてのAl膜6が選択的に
除去されている断面図を示す。以上のようにこの実施例
によれば アスペクト比の高いコンタクトホールでL 
カバレッジの良い多層配線の連結部を形成することが出
来 デバイスの信頼性の向上につながも 発明の効果 以上の実施例から明らかなように本発明によれば 溶融
したA1を直接にコンタクトホールに充填させるたべ 
今後のコンタクトホールの微細化に伴1.X、高速スパ
ッタ法のような従来の膜形成法に比べてコンタクトホー
ル部分での Alのステップカバレッジが良くなり、A
lの断線を防ぐことができ、コンタクト抵抗値も低減さ
れ デバイスの信頼性向上につながム
Furthermore, a metal film 7 having a melting point higher than that of A1 is formed as a lower layer wiring film on top of the metal film 7. Sputter deposition may be used to form the high melting point metal film 7. A high melting point metal 7 is used as a lower wiring film, and an interlayer insulating film 9 of about 800 nm is formed thereon, and this is dry etched using, for example, a resist as a mask to form a contact hole to expose the lower wiring film. Next, a metal film 7 having a melting point higher than that of Al is again formed on the interlayer insulating film 9, and a wiring pattern is formed by dry etching this using, for example, a resist as a mask. By applying the molten Al film 6, which will become the upper layer wiring film, by dropping A15 melted to about 700°C onto the rotated Si substrate 1 from the nozzle 11 while heating it to an appropriate temperature. Although the contact hole portion of the insulating film 9 is filled with Al, FIG. 3 is a cross-sectional view in which the Al film 6 as an upper wiring film is selectively removed in the contact hole portion of the interlayer insulating film 9. As described above, according to this embodiment, the contact hole with a high aspect ratio
According to the present invention, it is possible to form a connection part of multilayer wiring with good coverage, which leads to an improvement in the reliability of the device.Effects of the Invention As is clear from the above embodiments, according to the present invention, molten A1 is directly filled into contact holes. let's eat
With the future miniaturization of contact holes, 1. X. Compared to conventional film formation methods such as high-speed sputtering, the step coverage of Al in the contact hole area is better, and A.
This prevents disconnection of the l and reduces contact resistance, which improves device reliability.

【図面の簡単な説明】[Brief explanation of the drawing]

第1医 第2@ 第3図はそれぞれ本発明の第1、2、
3の実施例を示す半導体装置の製造工程断面図 第4図
は従来の実施例を示す半導体装置の半畳断面図であム ト・・81基板、 2・・・拡散# 3・・・S+02
罠 4・・・コンタクトホールL/、5・・・溶融した
Al、 6・・・Al罠 7・・・高融点金属膜 8・
・・シリサイドWL 9・・・層間絶縁[10・・・加
熱装rL 11・・・ノズノ―代理人の氏名 弁理士 
粟野重孝 はか1名第 第 図 図 第 第 図 図
1st doctor 2nd @ Fig. 3 shows the first, second, and third embodiments of the present invention, respectively.
Fig. 4 is a half-fold cross-sectional view of a semiconductor device showing a conventional embodiment. Mut...81 substrate, 2...Diffusion #3...S+02
Trap 4... Contact hole L/, 5... Molten Al, 6... Al trap 7... High melting point metal film 8.
...Silicide WL 9...Interlayer insulation [10...Heating device rL 11...Nozuno - Name of agent Patent attorney
Shigetaka Awano

Claims (3)

【特許請求の範囲】[Claims] (1)半導体基板の一主表面上に絶縁膜を形成した後、
前記絶縁膜を選択的に除去しコンタクトホールを形成す
る工程と、前記半導体基板表面に溶融したAlを塗布す
る工程からなり、Alと前記半導体基板とを電気的に接
続することを特徴とする半導体装置の製造方法。
(1) After forming an insulating film on one main surface of the semiconductor substrate,
A semiconductor comprising the steps of selectively removing the insulating film to form a contact hole, and applying molten Al to the surface of the semiconductor substrate, electrically connecting the Al and the semiconductor substrate. Method of manufacturing the device.
(2)コンタクトホールを形成した後、半導体基板表面
にAlより高い融点を有する所望の厚さの金属膜を形成
し、その後溶融したAlを塗布することを特徴とする請
求項(1)記載の半導体装置の製造方法。
(2) After forming the contact hole, a metal film of a desired thickness having a melting point higher than Al is formed on the surface of the semiconductor substrate, and then molten Al is applied. A method for manufacturing a semiconductor device.
(3)半導体基板の一主表面上に絶縁膜を形成した後、
前記絶縁膜を選択的に除去しコンタクトホールを形成す
る工程と、前記半導体基板表面にAlよりも高い融点を
有する下層金属配線膜を形成する工程と、前記下層金属
配線膜上に層間絶縁膜を形成し、これを選択的に除去し
てコンタクトホールを形成する工程と、前記半導体基板
上に上層配線膜となる溶融したAlを塗布し、前記コン
タクトホールを介して前記下層金属配線膜と上層配線膜
とを電気的に接続することを特徴とする半導体装置の製
造方法。
(3) After forming an insulating film on one main surface of the semiconductor substrate,
selectively removing the insulating film to form a contact hole; forming a lower metal wiring film having a melting point higher than Al on the surface of the semiconductor substrate; and forming an interlayer insulating film on the lower metal wiring film. forming and selectively removing it to form a contact hole, and applying molten Al that will become an upper layer wiring film on the semiconductor substrate, and connecting the lower layer metal wiring film and the upper layer wiring through the contact hole. A method for manufacturing a semiconductor device, the method comprising electrically connecting a semiconductor device to a film.
JP2215358A 1990-08-14 1990-08-14 Manufacture of semiconductor device Pending JPH0497530A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2215358A JPH0497530A (en) 1990-08-14 1990-08-14 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2215358A JPH0497530A (en) 1990-08-14 1990-08-14 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0497530A true JPH0497530A (en) 1992-03-30

Family

ID=16670972

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2215358A Pending JPH0497530A (en) 1990-08-14 1990-08-14 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0497530A (en)

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