JPH0498555A - Bus interface check system - Google Patents

Abstract

PURPOSE:To easily detect the area of a trouble by connecting a check circuit provided on a board containing a CPU to an external bus of a bus interface of the board and returning the deciding results of a prescribed pattern as well as a test pattern given from an external bus to an internal bus. CONSTITUTION:When the soundness of a check circuit 113 is confirmed, a test pattern of an internal bus 103 is fetched by the circuit 113 with a READ- DATA signal. If this test pattern is coincident with a prescribed pattern, the READ-DATA signal is applied to the circuit 113. Thus the logical truth is outputted as a check signal for the bus 103. When the soundness of a bus interface 109 is confirmed, a CPU 101 generates a test pattern and writes it into the circuit 113 with the WRITE-DATA and READ-DATA signals. Then the result of collation between the test pattern and the prescribed pattern is outputted. The CPU 101 fetches an external bus check signal which emerges on an external bus 105 and shows the result of collation between both patterns from the bus 103. Thus the true/false value of the bus check signal is observed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a bus driver/Rusino etc. (also referred to as a Nohes buffer) that transmits to and/or receives data from a bus via a bus interface. The present invention relates to a bus interface testing method for supporting fault self-diagnosis in a system including a plurality of boards connected to a bus.

[Prior art and its problems] As shown in FIG. 2, a CPU 201 sends and receives signals from board A on which it is riding to another board B via a motherboard 207 (or backplane). In a system configuration, it is desirable to be able to perform self-diagnosis when an abnormality is detected in the operation of the system, or at a specific point in time, such as when the power is turned on, even if no abnormality is detected.

Such self-diagnosis is usually performed by the CPU 20 on board A.
11) This is done by transmitting and receiving data, commands, etc. to and from other boards via the </< interface 209. However, since there is a possibility that the bus interface to the board on which the CPtJ that performs the diagnosis is riding may fail, when performing self-diagnosis, it is necessary to determine whether the problem is with your own board or with the other board. , it may not be possible to identify the location of the failure.

For example, if the bus interface 209 on board A or the bus interface 211 on board B fails and a malfunction occurs on the external bus 205, which of these two bus interfaces It was difficult to know if there was a disability.

Therefore, when taking measures for a problem with the external bus, it is not possible to know which board to replace, board 8 or board B, which is one of the reasons why failure repair efficiency is not improved.

[Object of the Invention] An object of the present invention is to provide a bus interface inspection method that can solve the problems of the prior art described above and easily isolate the fault location in a system configured as described above. shall be.

[Summary of the Invention] According to one embodiment of the present invention, a test circuit is provided on a board on which a CPU is mounted. This test circuit is connected to the external bus side of the bus interface of this board. The test circuit determines whether the test pattern applied via the external bus matches a predetermined pattern, and returns the result to the internal bus.

Furthermore, in order to diagnose whether the test circuit itself is healthy or not, the test circuit is also connected to an internal bus, from which a similar test pattern is input to determine whether or not it matches a predetermined pattern. Do it.

Furthermore, there is a possibility that a board connected to the external bus may malfunction due to the test pattern output onto the external bus while the test circuit itself is determining its health. Therefore, bus interfaces on other boards can be disabled during that time.

U Embodiment FIG. 1 is a diagram showing the main parts of a system to which an embodiment of the present invention is applied. In the same figure, board A has a CPU,
A bus interface 109 (bus driver/receiver) for bidirectional data transmission between the internal bus 103 on board A and the external bus 105 on the motherboard 107, and a test circuit whose operation will be explained below. 113 is provided.

The test circuit 113 has two data inputs, one of which is connected to the internal bus 103 between the CPUl0I and the bus interface 109, and the other is connected to the external bus 105 between the bus interface 109 and the bus connector (not shown). connected between. For these data inputs, WRJ
When data (test pattern) is written from the internal bus 103 or external bus 105 with the TE DATA signal set to true, the written test pattern matches one of several predetermined patterns and the READ
The configuration is such that if the DATA signal is true, either the external HAS CHECK signal or the internal BUS CHECK signal is true. The internal bus 103 check signal and the external bus check signal are each applied to a particular line of internal bus 103, eg, DO and Dl, respectively.

The testing procedure is to first check the health of the internal bus 103, then check the health of the test circuit 113, and then check the health of the bus interface 109. Once the health has been confirmed up to this point, it can be assumed that board A is operating normally in most cases, and after that, appropriate test operations can be performed from board A on the desired board.

The health of the internal bus 103 is determined by the internal bus 10 within board A.
3 can be easily checked by accessing the CPUIOI. For example, even if a special test procedure is not performed, if the CPU 10I accesses the display controller 115 on board A and a normal display is displayed on the display (not shown), the internal bus 103 will function normally. It can be considered to be working.

Next, the soundness of the test circuit 113 is confirmed. Test circuit 1
13 is controlled by a test circuit read/write circuit controlled by CPUl0I. Write signal READ DA from test circuit read/write circuit
The test pattern on the internal bus 103 is loaded into the test circuit 113 by TA. If the captured test pattern matches any of several predetermined patterns, the test circuit read/write circuit 117
By applying the READ DATA signal to the test circuit 113, a logical true signal is output as a check signal to the internal bus 103. Internal bus check signal is internal bus 1
03 (eg its 0th bit position Do). Furthermore, if it does not match any of the patterns, the internal bus check signal becomes false.

When checking the health of the test circuit 113, CPUl0
I controls the test circuit 113 at the timing shown in FIG. 3 by applying several types of test patterns onto the internal bus 103 and controlling the test circuit read/write circuit 117. This allows any test
If the expected true/false value of the internal bus check signal is obtained for the pattern (for example, if a test pattern that does not match any of the predetermined patterns is intentionally given, the internal bus check signal (the expected value of is false), it is confirmed that the test circuit 113 is healthy.

Using the test circuit 113 whose health has been confirmed in this way, the health of the bus interface 109 is then confirmed as follows.

A time chart of various signals for this confirmation is shown in FIG. As can be seen from FIG. 4, similar to the health check of the internal bus 103 shown in FIG. 3, the CPU OL generates various test patterns. This is the WRITE DA generated by the inspection circuit read/write circuit 117.
The TA signal and the RE and AD DATA signals are used to write to the test circuit 113, which outputs the results of comparison with a predetermined pattern. In checking the external bus 105, among the outputs of the test circuit 113, the external bus 105
The CPU 10I takes in an external bus check signal from the internal bus indicating the result of comparison with the test pattern appearing above, and observes its true/false value. If the true/false values match the expected values for all given test patterns, it is determined that the bus interface 109 is healthy.

If the inspection up to this point shows that the internal bus 103 and the inspection circuit 1
If it is found that there is an abnormality in either the board A or the bus interface 113, replace the board A. If there is no abnormality in any of these, it can be seen that the abnormality that has been discovered or will be discovered is on the board B side. In this case, by replacing board B, the device can be restored to a normal state.

In the above configuration, in some cases, the test circuit 11
There is a possibility that other boards may receive the test pattern for checking the health of the bus interface 109 on Board A or Board A, causing unexpected operation. To avoid this problem, as shown in FIG. 5, a bus interface disable circuit 121 is provided that generates a disable signal that forces the bus interfaces on other boards into a high impedance state. I can do it. Disable signal is motherboard 107
to the disable terminal of the bus interface on board B. The above-mentioned problem can be solved by performing the confirmation operation shown in FIG. 4 after the bus interface 111 on board B and the circuits beyond it are disconnected from the external bus 105 by the disable signal. FIG. 6 shows a time chart of various signals during the confirmation operation in the configuration shown in FIG. 5. Also, instead of disabling the bus interfaces on other boards, an address that is not used elsewhere may be assigned as the address for the test circuit 113.

The bus disable circuit described above is particularly useful in testing bus interfaces for address buses. It is a test circuit 113 for address/noise.
In order to check the health of the board, it is necessary to output several test patterns onto the address bus, and it is possible that these patterns may coincide with the input/output address of one of the boards.

Further, even when a plurality of boards are connected to the external bus 105, a configuration as shown in FIG. 7 can be adopted.

In this way, once the health of the main board to be inspected, here board A, is confirmed, the entire device can be inspected using well-known methods such as sending appropriate test patterns to other boards. .

In other words, except for the rare situation where two or more of the bus interface on the board to be tested, the test circuit, and the board to be tested fail at the same time, the present invention makes it possible to identify the failure location. .

Note that it is desirable that the above-mentioned test circuit be integrated into one or a small number of chips. This is because such integration reduces the probability that the test circuit itself will fail, and also increases the correlation between failures in the internal bus check section and the external bus check section within the test circuit. This is because the reliability of the method for confirming the health of the test circuit, in which the soundness of the test circuit including the part that tests the test pattern on the external bus is confirmed by the test, is increased.

Also, the bus interface may be bidirectional or unidirectional.

[Effects of the Invention] As described in detail above, according to the present invention, a faulty board can be quickly identified, thereby shortening the time required to replace such a board and recover from a device fault. be able to.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing a system configuration to which the present invention can be applied, and FIGS. 3 and 4 are diagrams showing the operation of the embodiment of FIG. 1. Timing Charts FIG. 5 and FIG. 7 are diagrams each showing another embodiment of the present invention, and FIG. 6 is a timing chart showing the operation of the embodiment of FIG. 5. 101: CPU 103: Internal Bus 05: External Bus 107: Motherboard 109.111: Bus Interface 113: Test Circuit 115: Display Controller 117: Test Circuit Read/Write Circuit 119: Control Bus 12I: Bus Interface Disable circuit

Claims (2)

[Claims] (1) In a bus interface inspection method for a device that includes a first board and a second board interconnected by an external bus, the first board has a bus interface that interfaces with the internal bus and the external bus. The test circuit includes an interface and a test circuit, and the test circuit compares the test pattern output on the internal bus with a predetermined pattern and outputs a first signal indicating the presence or absence of a match; Comparing the test pattern output on an external bus with a predetermined pattern, outputting a second signal indicating the presence or absence of a match, and confirming the soundness of the test circuit using the first signal. . A bus interface inspection method, characterized in that the soundness of the bus interface is confirmed by the second signal. (2) The first board is connected to the bus on the second board.
the second signal disabling the interface;
2. The bus interface testing method according to claim 1, wherein the bus interface testing method is applied to a board.