JPH0793225A - Memory check method - Google Patents

Abstract

(57) [Summary] [Object] The present invention reliably detects if there is an abnormality in even one bit of an address or data. [Structure] The memory controller (4) creates data of the number of bits, which is a combination of the address information and the data issued from the CPU (1), and masks this data based on the address information and the data The parity is taken to generate check data that affects each of the three bits of the data, and this check data is stored in the check memory (9). After that, the data stored in the data memory (7) is read and the consistency between this data and the check data is checked to perform a memory check.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory check system for detecting a memory abnormality in an electronic computer.

[0002]

2. Description of the Related Art As a method of testing such a memory, the same data is written in all areas to be tested in the memory, and then the memory is checked by checking whether the same data is read.

According to this check, if the data line has an abnormality such as a disconnection or the memory cell has an abnormality, the same data as the data written in the memory is not read and is detected as an abnormality.

On the other hand, a method of detecting an abnormality of a memory in a computer in operation is to provide a memory for holding check data in addition to the data and write the check data generated from the data at the time of writing operation to the memory for holding the data.
During the read operation, the memory abnormality is detected by hardware-checking the consistency between the read data and the check data.

However, although these memory testing methods can detect abnormalities in data lines, it is difficult to detect abnormalities in addresses. For example, when a specific address line is cut off or a plurality of address lines are short-circuited, even if the address line is abnormal, the same data as the written data is read out, so that it is detected as normal.

[0006]

As described above, according to the above-mentioned memory testing method, the abnormality of the data line can be detected, but it is difficult to detect the abnormality of the address. Therefore, an object of the present invention is to provide a memory check system capable of surely detecting an abnormality in even one bit in an address or data.

[0007]

According to a first aspect of the present invention, check data is applied to each bit of data by applying a mask pattern that affects an arbitrary number of bits of the data based on address information. Is generated, and the memory is checked by reading / writing the memory with this check data to achieve the above object.

According to a second aspect of the present invention, data having the number of bits in which the address information and the data are combined is created, the data is masked based on the address information and the data, and the even parity is taken to obtain the data. This is a memory check method that achieves the above object by generating check data that affects an arbitrary number of each bit, and reading / writing the memory by this check data to perform a memory check.

[0009]

【Example】

(1) The first embodiment of the present invention will be described below. Address information is used as a generation source of check data. Each bit of this check data is a plurality of bits of parity data extracted from the address information. At this time,
The check data is generated by a mask pattern in which each bit of the address information affects the data of three or more odd-numbered bits having different check data.

For example, when the address information and the data are both 8 bits, as an example of the method of generating the data used for the memory test, each bit is subjected to the following mask pattern for the address information and the even parity is taken. And

[Data] [Mask] Bit 7: 00010101 Bit 6: 01000101 Bit 5: 0101010001 Bit 4: 01010100 Bit 3: 10101000 Bit 2: 10100010 Bit 1: 10001010 Bit 0: 00101010 In this mask pattern, each address information is Each bit has an effect on the 3-bit parity generation of the data.

Here, the address information is, for example, "0000".
If it is 0001 ", masking each bit of this address and data (if the AND of the address information and the mask is taken), the data becomes" 1 "only for each bit 7, 6 and 5, and the rest All of the bits 4, 3, 2, 1, 0 are “0”.

Therefore, the written check data is "11100000". The check data thus generated is written in the entire area of the memory to be tested, and then read from the memory and used for checking.

Since each bit of the address affects the odd number of data of 3 or more of the check data as described above, if the address is abnormal,
Abnormality is detected in an odd number of data bits.

At this time, if the mask pattern at the time of generating the check data is viewed in reverse, it is possible to specify which address has an abnormality. If one bit of data is abnormal,
It is detected as a 1-bit abnormality in only that data bit.

Further, when 2 bits of the address and the data are abnormal, an abnormality is detected in an even number of data bits, so that it is possible to judge that there is an abnormality in this case as well.

For example, a case where the bit 0 of the address is fixed in the state of being "0" will be described. Even if the address is "00000000" at this time, it is also "0".
Even if "0000001", bit 0 of the address is "
Since it is fixed to 0 ", access to the address" 00000000 "is made on the memory regardless of the address.

Therefore, the check data is the address "
The data already written in "00000000" will be overwritten. Therefore, the address "000000" will be overwritten.
01 "is written at the address" 0000000
If it is performed after the writing to 0 ", the check data for the address" 00000001 "is read at the time of the read check for the address" 00000000 "even though the address is" 00000000 ".

At this time, if the check data are compared, three bits are detected as abnormal in each of the bits 7, 6 and 5. Therefore, if the mask pattern is subtracted in reverse, it is detected that the bit 0 of the address is abnormal because the bit 0 of the address is involved in the generation of the bits 7, 6, and 5.

Even when other bits become abnormal, the abnormal portion can be easily identified in the same manner. As described above, according to the first embodiment, it is possible to detect an abnormality not only in the data but also in the address information and identify the abnormal portion. (2) Next, a second embodiment of the present invention will be described.

FIG. 1 is an overall configuration diagram of a memory controller with an address abnormality detection mechanism to which a memory check method is applied. CPU1 includes a CPU address line 2 and a CPU
The memory controller 4 is connected via the data line 3.

A data memory 7 is connected to the memory controller 4 via a memory address line 5 and a memory data line 6, and a check memory 9 is connected via a memory address line 5 and a check data data line 8. It is connected.

The memory controller 4 creates data of a bit number which is a combination of the address information and the data issued from the CPU 1, masks this data based on the address information and the data, and takes the even parity. Check data that affects each of the three bits of the data is generated, the check data is stored in the check memory 9, and thereafter, the data stored in the data memory 7 is read to obtain the check data and the check data. It has the function of checking consistency and performing memory check.

Further, the memory controller 4 has a function of sending an interrupt signal 10 such as an error notification signal to the CPU 1 to notify the occurrence of an abnormality when an abnormality is detected as a result of the memory check. .

Next, the memory check in the memory controller configured as described above will be described. The memory controller 4 generates check data to be written in the check memory 9 from the data stored in the data memory 7 and the corresponding memory address information. That is, the memory controller 4 combines the address information and the data issued from the CPU 1 and regards the address information and the data as data of the total number of bits.

For example, if the address information is 10 bits and the data is 8 bits, it is regarded as 18 bits of data in total, and check data is generated from this data.

As a specific example, both address information and data are 8
When the bit data memory 7 is connected, 6 bits are used as the check data at this time, and the check data is generated by the following mask pattern.

[0028] Then, for example, when the address information is “1” and the data is “2”, masking is performed and the even parity is taken as follows.

Bit 5: (11101101_00110100) AND (00000001_00000010) = 00000001_00000000 ... 1 Bit 4: (11011010_10101010) AND (00000001_00000010) = 00000000_00000010 ... 1 Bit 3: (10110110_01011001) AND (00000001_00000010) = 00000000_00000000 ... 0 Bit 2: (01110001) ) AND (00000001_00000010) = 00000001_00000010 ... 0 Bit 1: (00001111_11000000) AND (00000001_00000010) = 00000001_00000000 ... 1 Bit 0: (00000000_00111111) AND (00000001_00000010) = 00000000_00000010 ... 1 From this result, the check data becomes "110011" .

The memory controller 4 stores the check data thus obtained in the corresponding check memory 9
When the data is read out, the consistency between the data memory 7 and the address information and the check data is checked.

Since each bit of the address information and data affects the odd number of bits of the check data, if one bit of the address information is accessed in the wrong state, the odd number of the check data will be detected. Abnormality is detected in each bit. Then, which bit has an error is specified by the pattern of the check data.

For example, when the address "1" is supposed to be read but the address "0" is read due to some abnormality, the check data involved in the generation of the address "1" is stored in the corresponding bits, that is, bits 1, 2, and 5. A parity error will be detected.

When this bit pattern is collated with the mask pattern at the time of generation, it is 0 bit of the address information that is involved in the parity generation of bits 1, 2 and 5, whereby the location of the abnormality can be specified.

When the abnormality is detected in this way, the memory controller 4 sends an interrupt signal 10 such as an error notification signal to the CPU 1 to notify the occurrence of the abnormality.
If any two bits of the address information or the data are abnormal, the even number of bits of the check data is detected to be abnormal. Therefore, it is not possible to specify which bit is abnormal, but the abnormality can be detected. .

As described above, according to the second embodiment, if even one bit of the address or the data is abnormal, it can be reliably detected and the memory controller 4 in operation.
At, the data memory 7 can be checked.
The present invention is not limited to the above embodiments, and may be modified without changing the gist thereof.

[0036]

As described above in detail, according to the present invention, if even one bit of an address or data is abnormal,
A memory check method capable of surely detecting this can be provided.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram of a memory controller with an address abnormality detection mechanism to which a memory check method according to the present invention is applied.

[Explanation of symbols]

1 ... CPU, 2 ... CPU address line, 3 ... CPU data line, 4 ... memory controller, 5 ... memory address line,
6 ... Memory data line, 7 ... Data memory, 8 ... Check data data line, 9 ... Check memory.

Claims (2)

[Claims] 1. A check pattern is generated by applying a mask pattern to each bit of data, which affects an arbitrary number of bits of the data, based on address information.
A memory check method characterized by performing a memory check by reading / writing to the memory based on this check data. 2. A data having a number of bits, which is a combination of address information and data, is created, a mask based on the address information and the data is applied to the data, and the even parity is taken to obtain each of an arbitrary number of the data. A memory check method characterized in that check data that affects bits is generated, and the memory is read / written by this check data to perform a memory check.