JPH0499331A - semiconductor equipment - Google Patents

Abstract

PURPOSE:To enable element area to be reduced by constituting a Schottky barrier diode by achieving ohmic contact to a P-type base region and Schottky contact with an N-type semiconductor layer by utilizing a side surface of a metal layer which is buried at a recessed part. CONSTITUTION:For forming a metal layer 8 which is buried into a recessed part 7, the recessed part 7 is provided by selectively etching an N-type epitaxial layer 3 by an anisotropic dry etching method, the metal layer 8 with a low specific resistance is allowed to grow at a front including the recessed part 7 by the vapor growth method, and then the metal layer 8 is left only within the recessed part 7. A three-dimensional Schottky barrier diode SBD where contact area with the N-type epitaxial layer 3 is achieved by utilizing a side surface of the metal layer 8 and a Schottky barrier diode with a small operation resistance can be constituted by securing a required Schottky contact area even if an area in plane direction in the metal layer 8 is reduced.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device, and particularly to an NPN device having a Schottky barrier diode that realizes high-speed switching operation.
The present invention relates to the structure of type bipolar transistors.

[Conventional technology]

Conventionally, in order to realize high-speed switching operation in bipolar transistors, NPN
A Schottky barrier diode SBD is connected between the base and collector of the NPN type bipolar transistor TR.
A circuit configuration is used that prevents the type bipolar transistor from becoming excessively saturated when it is in the on state.

As a conventional structure for realizing this circuit configuration in an integrated circuit, there is a structure whose plan view is shown in FIG. 3(a) and its c-cg sectional view is shown in FIG. 3(b). That is, in these figures, an N° buried region 2 is formed in a P-type semiconductor substrate 1, and an N-type epitaxial layer 3 is formed thereon. In this N type epitaxial layer 3, a P type base region 4, an N' type emitter region 5, and an N' type collector contact region 6 are formed.

Further, the insulating film 9 provided on the N-type epitaxial layer 3 is partially removed, and the lower surface of the base electrode 12, which is partially overlapped with the P-type base region 4, is brought into contact with the N-type epitaxial layer 3 to form a Schottky barrier. A Schottky barrier diode SBD formed thereby is connected between the base and collector of the NPN bipolar transistor.

Note that 10 is an emitter electrode and 11 is a collector electrode.

[Problems to be Solved by the Invention] This conventional structure uses the base electrode 12 to form a Schottky barrier diode in a planar manner, so it is difficult to create a Schottky barrier diode with low operating resistance required for high-speed switching operation. To realize this, it is necessary to increase the area in which the N-type epitaxial layer 3 and the metal layer of the base electrode 12 are in contact with each other in plan view. Therefore, there is a problem in that the element area of this type of NPN bipolar transistor increases, and the area of the entire chip increases.

In addition, when the element area is large, the N' buried region 2 required to reduce the collector resistance of the NPN bipolar transistor and the operating resistance of the Schottky barrier diode becomes large, and the N' buried region 2 and the P-type semiconductor Board 1
Since the parasitic capacitance generated between them becomes large, this has a disadvantage in high-speed switching operation.

An object of the present invention is to provide a semiconductor device having an NPN bipolar transistor capable of high-speed operation with a reduced element area.

[Means to solve the problem]

The semiconductor device of the present invention includes an N-type semiconductor layer as a collector region having a highly doped buried region, a P-type base region formed in this N-type semiconductor layer, and an N-type emitter formed in this P-type base region. a recess provided from the surface of the N-type semiconductor layer in contact with the P-type base region; and in the recess, the recess is in ohmic contact with the P-type base head and forms a Schottky barrier with the N-type semiconductor layer. and a metal layer.

[Effect]

According to the present invention, ohmic contact with the P-type base head and Schottky contact with the N-type semiconductor layer are formed by using the side surfaces of the metal layer buried in the recess, and the contact area of these is increased. This makes it possible to obtain an element with a small planar area.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows an embodiment of the present invention, in which FIG. 1(a) is a plan view and FIG. 1(b) is a sectional view taken along the line A--A.

In these figures, an N-type buried region 2 is selectively formed in a required region of a P-type semiconductor substrate 1, and an N-type epitaxial layer 3 is grown on this buried region 2. A P-type base region 4 is formed in this N-type epitaxial layer 3, and an N''-type emitter region 5 is further formed within this P-type base region 4, thereby configuring an NPN bipolar transistor. Note that 6 is an N° type collector contact region formed at the same time as the N° type emitter region 5.

Further, from the surface of the N-type epitaxial layer 3, the P
A recess 7 is formed in contact with the mold base head 4, and in this recess 7 there is formed an ohmic contact with the P-type base region 4 and a mucous contact with the N-type epitaxial layer 3 to form a Schottky barrier. , a metal layer 8 of, for example, aluminum is buried therein. The upper surface of this metal layer 8 protrudes above the surface of the N-type epitaxial layer 3 and is configured as a base electrode.

To form the metal layer 8 embedded in the recess 7, the N-type epitaxial layer 3 is selectively etched using an anisotropic dry etching method to form the recess 7, and then a low ratio layer is formed using a vapor phase epitaxy method. A method can be adopted in which the resistive metal layer 8 is grown over the entire surface including the recess 7, and then the metal layer 8 is left only within the recess 7.

Here, the impurity concentration of P-type base region 4 and the impurity concentration of N-type epitaxial layer 3 are conventionally selected so as to form an ohmic contact and a Schottky barrier with respect to metal layer 8, respectively.

Note that 9 is an insulating film, and 10 and 11 are an emitter electrode and a collector electrode, respectively, which can be formed at the same time as the metal layer 8 as the base electrode.

According to this configuration, by embedding the metal layer 8 in the recess 7 provided in the N-type epitaxial layer 3, the side surface of the metal layer 8 is utilized to increase the contact area with the N-type epitaxial layer 3. A Schottky barrier diode SBD is realized. Therefore, even if the area of the metal layer 8 in the planar direction is reduced, the required Schottky contact area can be ensured and a Schottky barrier diode with low operating resistance can be constructed.
) It becomes possible to reduce the area of the element including the transistor.

Furthermore, since the area of the metal layer 8 in the planar direction is small, the area of the N-type buried region i2 formed in the lower layer can also be made small, and the N
Parasitic capacitance between the embedded region 2 and the P-type semiconductor substrate 1 is reduced to enable high-speed switching operation.

FIG. 2 shows another embodiment of the present invention, and FIG.
is a plan view, and FIG. 3(b) is a sectional view taken along the line B-B. Note that the same reference numerals are given to parts equivalent to those in the above embodiment.

In this embodiment, a recess 7 is provided in the N-type epitaxial layer 3 all around the P-type base region 40, and a metal layer 8 is buried therein, thereby forming a buried Schottky barrier diode.

According to this embodiment, although the element area is somewhat increased compared to the previous embodiment, it has the advantage that the operating resistance of the Schottky barrier diode SBD can be made small, which may be advantageous depending on the required characteristics.

[Effects of the Invention] As explained above, the present invention makes ohmic contact with the P-type base region by utilizing the side surface of the metal layer embedded in the recess,
In addition, since the Schottky barrier diode is configured in Schottky contact with the N-type semiconductor layer, the Schottky barrier diode with low operating resistance can be configured without increasing the plane area, and the device area can be reduced.

In addition, the area of the heavily doped buried region can be reduced as well as the planar area, the parasitic capacitance with the N-type semiconductor layer can be reduced, and faster switching operation can be obtained.

[Brief explanation of drawings]

FIG. 1 shows one embodiment of the present invention, FIG. 1(a) is a plan view, FIG. , V(a) is a plan view, and the same figure (
b) is a cross-sectional view taken along line B-B, and Figure 3 is a conventional NP.
FIG. 4A is a plan view of an N bipolar transistor, FIG. 4B is a sectional view taken along line C--C, and FIG. 4 is a circuit diagram of a bipolar transistor designed to increase speed. 1... P-type semiconductor substrate, 2... N'-type buried region 3
... N type epitaxial layer, 4... P type base region, 5... N'' type emitter region, 6... N'' type collector contact SN region, 7... recess, 8... metal layer(
base electrode), 9... insulating film, 10... emitter electrode, 11... collector electrode, 12... base electrode. Figure 1 (b) Figure 4

Claims (1)

[Claims] 1. N as a collector region with a high concentration buried region
-type semiconductor layer, a P-type base region formed in this N-type semiconductor layer, an N-type emitter region formed in this P-type base region, and provided in contact with the P-type base region from the surface of the N-type semiconductor layer. 1. A semiconductor device comprising: a recessed portion; and a metal layer within the recessed portion that is in ohmic contact with the P-type base region and forms a Schottky barrier with the N-type semiconductor layer.