JPH0499353A - Integrated circuit - Google Patents

Abstract

PURPOSE:To increase the contact area between wiring regions and thus decrease the effective contact resistance by forming a hole overlapping first wiring regions, and connecting the first wiring regions with a second wiring region through the hole. CONSTITUTION:A low-resistivity material, such as aluminum, is deposited on a semiconductor substrate 1 to form first wiring regions 2A and 2B separated with the minimum spacing that is determined by resolution. A hole 4 is formed overlapping the two regions 2A and 2b. A second wiring region 5 is formed on the hole 4 to connect the wiring regions 2A and 2B; that is, the second wiring region comes in contact with the side edges of the first wiring regions. If the area of the hole is the same, therefore, the effective contact area becomes large, and thus the contact resistance is decreased.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to a semiconductor integrated circuit device, and in particular, a first wiring region is formed in a plurality of islands, and the first wiring region is connected to a second wiring region. The present invention relates to a semiconductor integrated circuit device with a semi-custom configuration that is arbitrarily connected by wiring areas.

[Prior Art] Currently, semi-custom integrated circuits (hereinafter referred to as ICs) mainly consisting of CMOS gate arrays are in use.

In this type of IC, wiring patterns are designed for each type of wafer on which a large number of elements such as MOS transistors are formed so as to realize a desired circuit configuration. Therefore, after designing this wiring pattern, any IC can be completed in a short period of time simply by forming a wiring area based on the wiring pattern on the wafer. Normally, it is only necessary to design the four processes of contact, first wiring, through hole, and second wiring for each product, which is advantageous in terms of cost and time compared to designing and manufacturing all processes. be.

However, recently, as these semi-custom ICs have evolved further, even the contact and first wiring processes, which were previously designed for each product type, have become common, and only the two processes of through-hole and second wiring formation are now designed for each product type. This method has come to be used.

In this method, the first wiring area is used as a fixed wiring (underbus wiring) in addition to being used as a terminal part of the element, and through holes and second wiring are provided at appropriate positions to connect with the element terminal. It realizes connections and connections between elements. For this reason, although there is a decrease in element placement density and a decrease in the degree of freedom in wiring compared to the conventional method,
There is an advantage that an IC can be obtained at the price and wiring formation period of 2.

In designing an IC using this method, only one layer can be freely wired, so it is important to increase the utilization rate of the first layer wiring. Therefore, this kind of IC
In this case, a very large number of connection parts between the first wiring and the second wiring are generated, and the connection between the first wirings is also performed using the second wiring.

Fig. 4 shows an example, and Fig. 4 (a) is a plan view;
Figure (b) is a longitudinal sectional view thereof. That is, in order to connect the two first wiring regions 2A, 2B, openings 4A, 4B are provided in the interlayer insulating film 3 on the respective regions, and the second wiring region 5 is formed across these openings.
The two first wiring regions 2A and 2B are connected.

[Problem to be solved by the invention]

In such a conventional connection structure, each of the openings 4A4B is provided to be included in the first wiring area, that is, to have a width smaller than the width of the first wiring area 2A, 2B. This is to prevent the semiconductor substrate 1 from being partially removed when forming the opening. As a result, in order to connect the two first wiring areas 2A and 2B, 2
Two openings 4A and 4B are required, and as a result, the number of openings equal to the number of first wiring regions is required.

Further, a second wiring region 5 is formed so as to cover these openings 4A and 4B, but this portion becomes a region through which other second wiring regions cannot pass.

For example, FIG. 5(a) shows a wafer in which a large number of first wiring regions 2 are formed in the shape of rectangular islands connected to various elements formed on a semiconductor substrate 1. FIG. 5(b) shows a state in which wires are wired using the portions 4' (4A, 4B) and the second wiring region 5.

In FIG. 5(b), if it is attempted to pass through the second wiring area 5A as shown by the chain line in this figure, the interval between the second wiring area 5 for connecting the first wiring area becomes narrower. It is impossible to pass through this part.

Therefore, in order to reduce these areas where wiring is not possible, it is necessary to make the strip-shaped area of the first wiring area 2 large. However, if the area of the chip is constant, increasing the area of the strip-shaped regions will reduce the number of strip-shaped regions, resulting in a problem that the degree of freedom in distribution lines will be reduced.

Further, since the opening 4' is provided with a minimum area, the resistance component of this portion cannot be ignored, and a considerably large contact resistance will occur in the wiring formed by connecting many first wiring regions.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device having a wiring connection structure that increases wiring flexibility and reduces contact resistance.

[Means to solve the problem]

The semiconductor integrated circuit device of the present invention includes a plurality of island-shaped first distribution areas electrically connected to various elements formed on a semiconductor substrate and arranged at minimum intervals;
an insulating film that covers the first wiring region and has an opening extending between the first wiring regions; and a second distribution area electrically connected to.

[Effect]

According to the present invention, by connecting the second wiring region to the first wiring region through the opening formed between the first wiring regions, the area of the opening and the second wiring region in the planar direction can be reduced. At the same time, the contact resistance is reduced by increasing the substantial contact area between the second wiring region and the first wiring region.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows a connecting portion between a first wiring area and a second wiring area according to the present invention, and FIG. 1(a) is a plan view, and FIG. 1(b) is a sectional view.

As the first wiring regions 2A and 2B, a low resistance material such as aluminum is selectively formed on the semiconductor substrate 1 with a minimum interval determined by the resolution. Thereafter, a glabellar insulating film 3 is formed on the surface, and the glabellar insulating film 3 is provided with the first wiring region 2A.

Openings 4 are opened so as to overlap each other over 2B. At this time, the insulating film 3 needs to be made of a different material from the semiconductor substrate 1, and the interlayer insulating film 3
It is necessary that a solvent be present so that the surface of the lower semiconductor substrate 1 is not etched when the opening 4 is formed in the etching.

Since the surface of the semiconductor substrate 1 is usually a silicon oxide film, it is possible to use a polyimide material as the glabellar insulating film 3 and an alkaline organic solvent as its solvent.

As a result, even if the opening 4 is formed in a region where neither of the first wiring regions 2A and 2B exists, the solvent will not etch the surface of the semiconductor substrate 1.

After providing the opening 4 so as to overlap the two first wiring regions 2A and 2B in this way, the opening 4. By forming the second wiring region 5 to cover the first wiring regions 2A and 2B, the first wiring regions 2A and 2B are electrically connected.

By adopting such a connection structure, the area of the second wiring region 5 in the planar direction becomes smaller. That is, the opening 4
Assuming that the dimensions of 1 side are 2 μm, the minimum interval between the first wiring regions 2A and 2B is 2 μm, and the opening 4 must be formed within 2 μm inside the first wiring regions 2A and 2B, It is assumed that the second wiring region 5 must be covered by 2 μm or more.

In the conventional connection structure, the size of the second wiring area required for connection between the first wirings at one location is at least 14 μm x 6 μm.
m. On the other hand, in the present invention, assuming that the amount of overlap between the opening and the first wiring area is 2 μm and other dimensions are the same as in the conventional case, the minimum size of the second wiring area is 1 μm.
The size is 0 μm×6 μm, which means that the area is reduced by about 30%.

On the other hand, in the present invention, since the side surface of the first wiring area is in contact with the second wiring area, if the area of the opening in the planar direction is the same, the actual contact area is thicker (or smaller). , the contact resistance between the two is reduced.

Similar to FIG. 5(a), FIG. 2(a) shows a wafer in which a plurality of strip-shaped island-shaped first wiring regions 2 are formed on a semiconductor substrate l. A glabellar insulating film is formed on this,
FIG. 2(b) shows a state in which wiring is done using the opening 3 and the second wiring area 5.

In FIG. 2(b), due to the reduction in the area of the second wiring region, the second wiring region 5A is arranged between other second wiring regions 5, which was impossible in FIG. 5(b). becomes possible. Thereby, by reducing the area of the second wiring region 5, the number of second wiring regions 5 can be increased, and the degree of freedom in wiring can be increased.

FIG. 3 shows a second embodiment of the present invention, with FIG. 3(a) being a plan view and FIG. 3(b) being an enlarged sectional view.

Here, the gate electrode of the silicon gate MO3) transistor is configured as the first wiring region. In the figure, an oxide film 12 is formed on a semiconductor substrate 11 to define an element region, and then a diffusion region 13 as a source/drain region is formed in the element region, and a gate is formed through a gate insulating film (not shown). The electrode 14 is made of polycrystalline silicon. Then, the glabella insulating film 15 provided on the gate electrode 14
An opening 16 is provided in which adjacent gate electrodes 14 are electrically connected to each other by a second wiring region (first layer metal wiring) 17.

In this way, by applying the present invention to the connection between the gate electrodes of MOS transistors, the area of the second wiring region can be reduced and the degree of freedom of wiring in the second wiring region can be increased.

〔Effect of the invention〕

As explained above, the present invention provides an opening in the insulating film between the first wiring regions, and a second wire through the opening.
Since the wiring areas are connected to the first wiring area, the area of the opening and the second wiring area in the planar direction is reduced, and the number of lines in the second wiring area is increased, increasing the degree of freedom in design. On the other hand, there is an effect that the substantial contact area between the second wiring region and the first wiring region can be increased and the contact resistance can be reduced.

[Brief explanation of drawings]

FIG. 1 shows the structure of the main part of the present invention, FIG. 1(a) is a plan view, FIG. 2(b) is a sectional view thereof, and FIG. Figure (a) is a plan view of the first wiring area, Figure (b) is a plan view of the second wiring area, Figure 3 shows a second embodiment of the present invention, and Figure (a) is a plane view. Figure 4 shows an example of a conventional wiring connection structure, Figure 4 (a) is a plan view, Figure 4 (b) is a cross-sectional view, and Figure 4 (a) is a plan view.
5 shows a semiconductor integrated circuit device using the technique shown in FIG. 4, FIG. 5(a) is a plan view of the first wiring area, and FIG. FIG. 1... Semiconductor substrate, 2A, 2B... First wiring region,
3... Interlayer insulating film, 4.4', 4A, 4B... Opening, 5.5A... Second wiring region, 11... Semiconductor substrate, 12... Oxide film, 13...・Diffusion header, 14...
・Gate electrode (first wiring region), 15... Interlayer insulating film, 16... Second wiring region Figure 1 Figure 2 (a) (a) Figure (a) (b) Figure 4

Claims (1)

[Claims] 1. A plurality of island-shaped first wiring regions electrically connected to various elements formed on a semiconductor substrate and arranged at minimum intervals; an insulating film having an opening extending between first wiring regions; and a second wiring region formed on the insulating film to cover the opening and electrically connecting the first wiring regions to each other. A semiconductor integrated circuit device comprising: