JPH0499358A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent damage to electrode contacts by using a chip configuration in which the cross section of a contact hole for connection to a first electrode region is substantially the same as the total cross section of a plurality of contact holes for connection to a second electrode region. CONSTITUTION:There are provided a contact hole 11 for connection to a gate electrode (first electrode region), and contact holes 21 and 22 for connection to a capacitor (a second electrode region). The contact holes 21 and 22 are composed actually of four holes with the same diameter, and the total area in contact with the capacitor is the same as the cross section of the contact hole 11. The contact hole 11 connects the gate electrode to a word line E1, while the contact holes 21 and 22, including the two others, connect the capacitor 7 to a ground line E2. A plurality of contact holes having insulating films of different thicknesses can be formed for the same etching time.

Description

[Detailed Description of the Invention] [Summary] Regarding a method for forming contact holes of different depths, thick contact holes and thin contact holes in an insulating film can be drilled almost simultaneously, and a method that prevents damage to the connection electrode surface is provided. For the purpose of a plurality of contact holes connected to the second electrode region, and a hole cross-sectional area of the single contact hole connected to the first electrode region and a plurality of contact holes connected to the second electrode neck region; The contact holes are characterized in that the total cross-sectional area of the contact holes is approximately the same.

The manufacturing method is a manufacturing method in which a contact hole is simultaneously formed in a first electrode region covered with a thick insulating film and a second electrode region covered with a thinner insulating film than the insulating film of the first electrode region, and a seed region. a single window is provided on the first electrode region, a plurality of windows are provided on the second electrode region, and
a step of covering a mask pattern having a pattern such that the cross-sectional area of the single window and the total cross-sectional area of the plurality of windows are approximately the same; The method is characterized in that it includes a step of simultaneously etching a window to form a contact hole.

[Industrial application field]

The present invention relates to a semiconductor device and a method of manufacturing the same, and particularly relates to structures of contact holes having different depths and a method of forming the same.

As semiconductor devices become smaller and more highly integrated, it has become necessary to form contact holes in insulating films of different thicknesses, and the present invention relates to a structure and manufacturing method for easily forming such contact holes. .

[Conventional technology]

Semiconductor devices such as ICs and LSIs are being miniaturized and highly integrated because they have the advantage of improving characteristics such as high-speed operation. When a wiring layer is formed on a surface with steps, a problem arises in that the thinner the wiring becomes, the more short circuits occur in the wiring, and the reliability of the semiconductor device is lowered. For this reason, when depositing an insulating film or wiring layer, a flattening method is used to reduce surface irregularities as much as possible.
This is also the reason why the (phosphorus silicate glass) film is reflowed (remelted) after being deposited.

In addition, as semiconductor devices become more highly integrated, the wiring layers formed on the substrate become more congested. This means that multilayer wiring, which is stacked in two or three layers, becomes necessary. In addition to using contact holes to connect the first wiring layer, there is a need for a method for connecting the first wiring layer and the third wiring layer using contact holes.

[Problem to be solved by the invention]

However, with advances in flattening technology on the substrate surface,
When a technology is needed to connect the first wiring layer and the third wiring layer by jumping over the first layer, contact holes are drilled in the vertical direction when forming the wiring. In the process of forming the contact trj'tt electrode, various problems occur due to the difference in the thickness of the insulating film.

As a conventional method for forming contact holes in insulating films having different thicknesses, a manufacturing method is generally used in which control is performed so that a contact hole with an appropriate diameter can be formed in the deepest insulating film.

However, if this is done, the contact hole formed in the shallow insulating film will be over-etched (excessive etching), damaging the electrode surface at that location, and the etching selectivity between the insulating film and the wiring will be reduced. The damage is particularly large when the wiring resistance is small, and even if a conductor is buried there for connection, the resistance at the connection interface will increase, and this increase in wiring resistance will impede high-speed operation.

FIG. 5 is a diagram illustrating the conventional problem, and this example is a partial cross-sectional view of a memory cell of a stacked type DRAM memory. In the figure, the symbol l indicates the silicon substrate 2, a field insulating film made of SiO2 (silicon oxide) Pl, 3 the gate electrode made of polycrystalline silicon film, 4 the source region, 5 the drain region, and 6 the SiO2 (silicon oxide) film. 7 is a capacitor, 8 is a PS deposited by vapor phase growth (CVD) method.
G film, CI indicates a contact hole connected to the gate electrode, and C2 indicates a contact hole connected to the capacitor. Therefore, the contact hole C1 of this memory cell serves to connect the gate electrode to the word line E1, and the contact hole C2 serves to connect the capacitor 7 to the ground line E2.

The problem here is how to form contact holes such as C1 and C2, and the contact hole C1 formed on the gate electrode is
Since the contact hole C2 is formed by drilling an insulating film consisting of only the PSG film 8, if the contact holes C1 and C2 are etched at the same time, The contact hole C2 is opened first, and the capacitor 7 on the connection electrode surface
The polycrystalline silicon that makes up the film will be overetched and damaged.

In order to prevent this polycrystalline silicon surface from being damaged, it is necessary to have an etching selectivity of 15 or more.
This is extremely difficult, and even if such a high selection ratio can be selected, it is unavoidable that there will be variations in film quality within the wafer and that some over-etching will occur locally.

The present invention solves these problems and is aimed at manufacturing a semiconductor device in which thick contact holes and thin contact holes in an insulating film can be opened almost simultaneously, thereby preventing damage to the connection electrode surface. This paper proposes a method.

[Means to solve the problem]

The problem is as shown in the embodiment diagram of FIG.
．． A single contact hole 11 is connected to the first it electrode region which is thickly coated with 6, and a plurality of contacts are connected to the first t8ieI region which is covered with an insulating film 8 which is thinner than the insulating film of the first electrode region. The hole cross-sectional area of a single contact hole connecting the holes 2122 and connecting the first to the seed region and the total hole cross-sectional area of the plurality of contact holes connecting to the second electrode region are approximately equal to each other. The problem is solved by semiconductor devices that are configured to be identical.

The manufacturing method is as shown in the example diagrams in FIGS. A plurality of windows 2 are provided on the second electrode region coated with an insulating film thinner than the second electrode region, and the cross-sectional area of the single window and the total cross-sectional area of the plurality of windows are applying a mask pattern having substantially identical patterns; and then simultaneously etching the single window and the plurality of windows to form contact holes 11.2122. It is characterized by being

[For production]

That is, the present invention utilizes the microloading effect in the dry etching method to simultaneously open a plurality of contact holes having different thicknesses in an insulating film using the same etching time. This allows contact holes of different depths to be drilled simultaneously, reducing damage to the connection electrode surface.

This micro loadin
g) Effect means that when etching is performed to create two holes with different diameters (cross-sectional areas), the amount of radicals reaching the bottom of the hole is different, and the hole with the larger diameter is etched deeper. , the effect becomes more pronounced when the gas pressure of the reaction gas is high.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS A detailed description will be given below by way of example with reference to the drawings. FIG. 1 shows a cross-sectional view of a semiconductor device according to the present invention. That is, this example is a stacked type DRA as in FIG.
This is a partial sectional view of a cell of M memory, and the same symbols are attached to the same parts as in FIG. 5. Other symbols 11 are contact holes (same as contact hole C1) connected to the gate electrode (first t8ieI region);
21 and 22 are contact holes connected to the capacitor (second electrode region). Although only 2L 22 of the contact hole connected to this capacitor is shown in the figure, a total of four contact holes with the same diameter are connected to the capacitor in plan view, and their total cross-sectional area is equal to the cross-sectional area of contact hole 11. equal. This is to make the wiring resistance of the contact holes the same, for example, contact hole 1
If the diameter of the hole 1 is 1 μmφ, then the diameter of each of the four holes such as the contact holes 2L and 22 connected to the capacitor is set to 0.5 μmφ. Then, the cross-sectional areas of the holes become equal, and in this way, the contact hole 11 connects the gate electrode to the word arrangement E1, and the contact hole 2L
22 and two other contact holes, a total of four contact holes, have a structure in which the capacitor 7 is connected to the ground wiring E2.

This reduces damage to the electrode surfaces of gate electrodes, capacitors, etc., and allows a plurality of contact holes in insulating films with different thicknesses to be simultaneously formed in the same etching time. This is due to the microloading effect as described above, and FIG. 2 is a diagram showing the microloading effect. In the figure, the vertical axis is the etching rate (etching speed), and the horizontal axis is the hole diameter of the contact hole. The data is obtained by etching a SiO□ film produced by thermal oxidation, and the larger the hole diameter, the faster the etching occurs. It is clearly shown that the larger the hole diameter, the deeper the etching.

By simultaneously drilling holes using this microloading effect, contact holes can be simultaneously drilled without increasing the number of manufacturing steps, and high-quality semiconductor devices can be manufactured without causing damage.

FIGS. 3(a) and 3(b) are cross-sectional views in the order of steps of the manufacturing method according to the present invention.

FIG. 3 (see al; this figure shows a field insulating film 2 made of a SiO□ film formed on a silicon substrate 1, a gate insulating film,
The gate electrode 3 is patterned to define a source region 4 and a drain region 5, and an insulating film 6 (thickness 1000
The capacitor 7 is formed by stacking (laminating) the capacitor 7, and then the PSG film with a thickness of 5000 is deposited on the entire surface using the CVD method.
This is a cross-sectional view after reflowing with SaO2 covered, and a resist film mask 30 is selectively formed thereon. This resist film mask 30 is a protective mask (mask pattern) for simultaneously drilling a single window 1 on the gate electrode and four windows 2 on the capacitor.

FIG. 3 (see BL; next, etching is performed by RIE (reactive ion etching) using fluorine (F)-based gas as a reaction gas. Then, the PSGSaO2 edge film 6 is etched and a contact hole 11 is formed. On the other hand, PSGSaO2 can be etched at the same time, and two contact holes 21, 22 and others can be formed at the same time.

Thereafter, a conductor such as polycrystalline silicon or high melting point metal silicide is filled in the contact hole to form a through-hole interconnection connected to the word interconnection El and the ground interconnection WE2.

FIG. 4 shows a schematic diagram of the RIE apparatus applied to the manufacturing method according to the present invention, in which symbol 41 is a reaction vessel, 42 is a wafer (silicon substrate), 43 is an upper electrode, 44 is a lower electrode, and 45 is a high frequency Power supply (frequency 400KH2) 46
is a gas inlet, and 47 is an exhaust port. In order to open the above contact hole, a reactive gas (CF4
+CHFt +Ar), the flow rate CF, :CHF3
:^r=80 : 80 : 800 sccm is flowed and the vacuum is maintained at about 2 Torr by exhausting the reactor.

In addition, the electrode spacing is 10 mm, and 1400 W is applied between the electrodes.
A hole can be made by applying high-frequency power.

In this way, it is possible to reduce damage to the contact VtN electrode surface and simultaneously drill multiple contact holes with different thicknesses of the insulating film in the same time, resulting in stable wiring with less fluctuation in wiring resistance. wiring can be formed.

Although the above embodiment is explained using an example in which one contact hole and four contact holes are formed at the same time, the present invention has a structure in which the number and hole diameter are varied according to the difference in etching depth. It is a manufacturing method.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, wiring with stable wiring resistance can be formed without increasing the number of manufacturing steps, and this greatly contributes to improving the quality reliability of semiconductor devices.

It shows.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a semiconductor device according to the present invention, FIG. 2 is a diagram showing the microloading effect, and FIG. 3 (al,
('I]) is a step-by-step cross-sectional view of the manufacturing method according to the present invention, FIG. 4 is a schematic diagram of an RIE apparatus, and FIG. 5 is a diagram explaining the problems of the conventional method. In the figure, 1 is a silicon substrate, 2 is a field insulating film, 3 is a gate electrode, 4 is a source region, 5 is a drain region, 6 is a gray film, 7 is a capacitor, 8 is a PSG film, 30 is a resist film Mask, C1, C2, 11, 21, 22 are contact holes, W
1, W2 is 971 years old.

Claims (2)

[Claims] (1) A single contact hole (11) is connected to the first electrode region covered with thick insulating films (8) and (6), and the insulating film (11) is thinner than that of the first electrode region. 8) a hole cross-sectional area of a single contact hole connecting a plurality of contact holes (21), (22) to the covered second electrode region and connecting to the first electrode region;
A semiconductor device characterized in that the total cross-sectional area of the plurality of contact holes connected to the second electrode region is approximately the same. (2) A manufacturing method in which a contact hole is simultaneously formed in a first electrode region covered with a thick insulating film and a second electrode region covered with an insulating film thinner than the insulating film of the first electrode region, , a single window (W1) is provided on the first electrode region, and a plurality of windows (W2) are provided on the second electrode region; a step of covering a mask pattern having a pattern such that the total cross-sectional area of the windows is almost the same, and then simultaneously etching the single window and the plurality of windows to form a contact hole (11). , (21) and (22).