JPH049999A - CRT display circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a CRT display circuit for displaying characters such as numbers and letters given from a microcomputer or the like in alignment over multiple lines on the screen of a CRT display device. It is something.

[Traditional techniques]

Part 3 shows a conventional example of a CRT display circuit for displaying characters on the screen of a CRT display device.

In FIG. 3, the CR7 display circuit 1 is connected to a CRT display device (
(not shown) is supplied with a rask scanning signal. The control microcomputer 2 is provided to control various operations of the CR7 display circuit 1, and for example, specifies a character to be displayed on the screen, and specifies the display position of the character in the horizontal and vertical directions. .

In the CRT display circuit 1, an interface 3 matches the control microcomputer 2 with the internal circuitry of the CRTR 7 display circuit. The timing generator 4 is a dot clock 12. Horizontal synchronization signal 13 and vertical synchronization signal 14
generate various timing signals for screen display using human power. A horizontal display start position control circuit 5 controls the horizontal display start position of each character in each display line on the screen. The vertical display start position control circuit 6A controls the vertical display start position of characters in each display line on the screen.

The video RAM 7 stores characters to be displayed on the screen in correspondence with the screen. Video RAM control circuit 8 controls writing and reading of video RAM 7. Character ROM
l0 stores data indicating the shape of the character,
It is accessed by successive data in the video RAM 7. The shift register 11 serially transfers the output of the character ROM10 to form a time-series signal. The CR7 display output circuit 9 outputs a CR7 display signal 25.

In the CRT display circuit 1 configured as described above, various data for display control is sent from the control microcomputer 2 to the timing generator 4 through the interface 3. The signal is sent to the horizontal display start position control circuit 5, the vertical display start position control circuit 6A, the video RAM 7 and the CR7 display output circuit 9.

The timing generator 4 is supplied with data such as character display size from the control microcomputer 2 through the interface 3 prior to character display on the screen. Similarly, the horizontal display start position control circuit 5 is supplied with data indicating the horizontal display start position of each character. Further, data indicating the vertical display start position of each character is given to the vertical display start position control circuit 6A. Data indicating the type of character to be displayed on the screen is provided to the video RAM 7 in correspondence with the screen and one sentence 11. The CR7 display output circuit 9 is supplied with data such as the display color of the character.

When the various data described above are sent from the control microcomputer 2 to the CRT display circuit 1, the timing generator 4 generates various timing pulses (for example, horizontal dot clock, vertical dot clock) necessary for displaying on the screen. , video RAM precharge, ROM precharge, data load signal from video RAM to shift register, etc.) to control the horizontal display start position control circuit 5.
．． Vertical direction display start position control circuit 6A, video RAM
Control circuit 8. The signal is supplied to the shift register 11.

The horizontal direction display start position control circuit 5 creates a signal indicating the horizontal direction display start position of each character to be displayed on the screen based on the timing pulse from the timing generator 4 and the horizontal synchronization signal 13. CR7 is sent to the display output circuit 9. In addition, the vertical direction display start position control circuit 6A
creates a signal indicating the vertical display start position of each display line character to be displayed on the screen, based on the timing pulse from the timing generator 4, the horizontal synchronization signal 12, and the vertical synchronization signal 14; CR7 display output circuit 9
send to

On the other hand, the video RAM control circuit 8 uses the timing generator 4
According to the timing pulse sent from the video R
The display data stored in AM7 is sequentially read out and sent to character ROM10. The character ROM 10 performs a read operation using the data sent from the video RAM 7 as an address, and sends the data to the shift register 11.

The soft register 11 converts the output data of the character ROM 10 into time-series data for CR7 display based on the timing pulse of the timing generator 4 and the signal indicating the horizontal display start position of the character given from the horizontal display start position control circuit 5. It is sent to the output circuit 9.

As a result, the CRT display display output circuit 9 creates a signal corresponding to the rask scan on the screen, sends it to the CRT display device (not shown), and displays the video RAM on the screen.
The character stored in 7 is displayed together with the background at a position defined by the horizontal display start position control circuit 5 and the vertical display start position control circuit 6A.

FIG. 4 shows a specific configuration of the vertical display start position control circuit 6A in the CRT display circuit shown in FIG. In FIG. 4, a counting circuit 15 uses the horizontal synchronization signal 13 as a clock (CK) input, the vertical synchronization signal 14 as a reset input, and counts the number of pulses of the horizontal synchronization signal 13 from the trailing edge of the pulse of the vertical synchronization signal 14 as a starting point. It has a function to count and detect the position of the horizontal scanning line currently being scanned on the screen.

The register 19 has N storage areas, and receives vertical display start position data indicating the vertical display start position of each of the first to Nth display lines of characters to be displayed on the screen using a vertical synchronization signal. The number of generated pulses of the horizontal synchronizing signal 13 up to the upper end of each display line from the first to the Nth line is stored with the trailing edge of the 14 pulses as a starting point. Specifically, as shown in FIG. The number of horizontal scanning lines included between the trailing edge (corresponding to the trailing edge) and the top of each display line L + -LN, that is, the vertical synchronization signal 1
Vertical direction display start position data ■P, ~vPN corresponding to the number of pulses of the horizontal synchronizing signal 13 from the trailing edge of the pulse No. 4 to the top of each display line L1 to LN are stored respectively. .

The multiplexer 18 converts any one of the vertical display start position data VP, ~VPN of each of the first to Nth display lines, ~L, stored in the register 19 into the line number data 20.
Select and output according to the following.

The data comparator 16 compares the output value of the counting circuit 15 and the output value of the multiplexer 18, and outputs a match signal 24 when the two match. A vertical display start signal generation circuit 17 consisting of a latch starts outputting a vertical display start signal 24 in response to a coincidence signal 24 output from the data comparator 16, and starts outputting a vertical display start signal 24 in response to a row display completion signal 21. The output of the start signal 24 is stopped.

Next, the vertical direction display start position control operation of this vertical direction display start position control circuit 6A will be explained.

In this vertical display start position control circuit 6A, after the counter circuit 15 is reset by the vertical synchronization signal 14, the counter circuit 15 counts the pulses of the horizontal synchronization signal 13, and increases the output value sequentially for each horizontal synchronization signal 13. let On the other hand, the multiplexer 18 selects any one of the vertical direction display start position data P1 to VPN in the register 19 according to the row number data and sends it to the data comparator 16.

Immediately after the trailing edge of the pulse of the vertical synchronization signal 14, the row number data 20 indicates the display row of the first row (first row), and the vertical direction display start position data VP of the display row L1 of the first row is data. Since the signal is sent to the comparator 16, a match signal 24 is generated when the output value of the counting circuit 15 matches the vertical display start position data vP1, and the vertical display start signal 22 is output from the vertical display start signal generation circuit 17. Start. This vertical display start signal 22 is then sent to the video RAM control circuit 8 and the CRT display output circuit 9 (see FIG. 3), and the display of the gear clutter in the display row L1 is started. Thereafter, when the row display completion signal 21 given from the timing generator 4 (see FIG. 3) is input to the vertical direction display start signal generation circuit 17, the output of the vertical direction display start signal 22 is stopped, and the display row L1 Complete the display of the character.

Next, the line number data 20 is changed to data indicating the second display line L2, and the vertical display start position data VP of the second display line L2 is sent to the data comparator 16. The characters in the display line L2 are displayed from the position corresponding to the vertical direction display start position data V P 2.

Thereafter, the line number data 20 is sequentially changed, and the characters in each display line L3 to Ls of the third to Nth lines are sequentially displayed from the position corresponding to the vertical display start position data vP3 to VP4.

The above operations are repeated for each frame, and the video R
If the contents of AM7 are not changed, the same character will be displayed on the screen P over a plurality of frames.

[Problem to be solved by the invention]

However, according to such a configuration, as in the case of performing vertical scrolling on the screen P, all display lines L on the screen P
When it is necessary to change the vertical display start position of 1 to L8, the control microcomputer 2 that controls the CR7 display circuit 1 performs full display and outputs -LH vertical display start position data V P + ~vP8 must be transferred to the CR7 display circuit 1. In the case of vertical scrolling, this transfer is required once for each frame of the display screen, which poses a problem in that it places a heavy burden on the control microcomputer 2.

Therefore, an object of the present invention is to provide control for rewriting vertical display start position data when uniformly changing the vertical display start positions of all display lines on the screen, such as when performing vertical scrolling. An object of the present invention is to provide a CRT display circuit that can reduce the burden on a microcomputer.

[Means to solve the problem]

The CRT display circuit of the present invention provides the number of pulses of a horizontal synchronization signal from a vertical synchronization signal as a starting point to the vertical display start position of the first display row on the screen as vertical display start position data of the first display row on the screen. The value corresponding to the vertical direction display start position data of each display line from the second line onward is stored, and the horizontal direction from the fixed position of the previous display line as the starting point to the vertical display start position of the relevant display line is stored. a register that stores a value corresponding to the number of pulses of the synchronizing signal; a counting circuit that is reset at each starting point and counts the number of pulses of the horizontal synchronizing signal; and an output value of the counting circuit and the corresponding value stored in the register. a data comparator that compares vertical display start position data corresponding to a display row; and a vertical display start that generates a vertical display start signal for the display row in response to generation of a match signal from the data comparator. The vertical direction display start position control circuit is comprised of a signal generation circuit.

[For production]

According to the configuration of the present invention, when it is necessary to change the vertical display position of all display lines equally, such as when performing vertical scrolling on the screen, the control is not performed as in the conventional method. It is not necessary to transfer the vertical display start position data of all display row bones from the microcomputer to the register that stores the vertical display start position data of each display line, but only the vertical display start position data of the first row is transferred. This makes it possible to uniformly change the vertical display position of all display lines by simply changing the vertical display position. For example, when performing vertical scrolling on the screen, the burden on the control microcomputer can be significantly reduced when rewriting vertical display start position data. can.

〔Example〕

An embodiment of the present invention will be described based on FIGS. 1 and 3. This CRT display circuit uses a vertical display start position control circuit 6B shown in No. 1 [iJ] in place of the vertical display start position control circuit 6A shown in FIG. 4, and the overall configuration is the same as that of the conventional example. It is similar to FIG.

In FIG. 1, the counting circuit 15 receives the horizontal synchronizing signal 13 as a clock (CK) input, uses the OR signal from the OR circuit 23 of the vertical synchronizing signal 14 and the row display completion signal 21 as a reset input, and uses the pulses of the vertical synchronizing signal 14 as a reset input. trailing edge and first
The number of horizontal synchronizing signals 13 from the bottom of each display line to the N-1th line to the top of each display line L1 to LH of the 1st to N-th line is calculated from the bottom of LM-1. It has a function of counting and detecting the position of the horizontal scanning line currently being scanned on the west surface (position based on the trailing edge of the pulse of the vertical synchronizing signal 14 or the lower end of the previous line).

The register 19 has N storage areas, each display row of the first to Nth rows of characters to be displayed on the screen,
- Vertical display start position data indicating the vertical display start position of LN is displayed for the first display line L1 using the trailing edge of the pulse of the vertical synchronization signal 14 as the starting point, and horizontal synchronization up to the top end is performed. The number of generated pulses of the signal 13 is stored, and for each of the second to Nth display lines L2 to L, the horizontal synchronization signal 13 is generated from the bottom end of the previous line as the starting point to each display line L2 to LH. It is memorized by the number of pulses. Specifically, as shown in FIG. The number of horizontal scanning lines included from the starting point (corresponding to the trailing edge of the pulse) to the top end of the first display line L1, that is, the horizontal synchronizing signal 13 calculated from the trailing edge of the pulse of the vertical synchronizing signal 14 vertical direction display start position data vP corresponding to the number of pulses is stored, and
The number of horizontal scanning lines included between the bottom end of the display line Ll-LH-1 and the top end of each display line L2 to L, I of the second to Nth rows, that is, the display line Ll- LH-
This means that vertical direction display start position data VQ, to VQH corresponding to the number of pulses of the horizontal synchronizing signal 1j counted from the lower end of 1 are stored, respectively.

The multiplexer 18 selects one of the vertical display start position data VP, , VQ, ~vQN of each of the first to Nth display lines LI-LN stored in the register 19 according to the line number data 20. and output it. The data comparator 16 compares the output value of the counting circuit 15 and the output value of the multiplexer 18, and outputs a match signal 24 when the two match.

The vertical direction display start signal generation circuit 17 consisting of lunch is
In response to the match signal 24 output from the data comparator 16, output of the vertical direction display start signal 24 is started, and in response to the row display completion signal 21, output of the vertical direction display start signal 24 is stopped.

Next, the vertical direction display start position control operation of this vertical direction display start position control circuit 6B will be explained.

In this vertical direction display start position control circuit 6B, after the counter circuit 15 is reset by the vertical synchronization signal 14, the counter circuit 15 counts the pulses of the horizontal synchronization signal 13, and increases the output value sequentially for each horizontal synchronization signal 13. and its output value is
It is also reset every row display completion signal 21. On the other hand, the multiplexer 18 controls the register 19 according to the row number data.
Vertical direction display start position data V P + , V
Select one of Q t to vQN and use the data comparator 16
send to

Immediately after the trailing edge of the pulse of the vertical synchronization signal 14, the row number data 20 indicates that the first row is to be displayed, and the vertical direction display start position data Pl of the display row L+ is sent to the data comparator 16. When the output value of the counting circuit 15 matches the vertical direction display start position data vp, a coincidence signal 24 is generated, and the vertical direction display start signal generation circuit 17 starts outputting the vertical direction display start signal 22. Display start signal 2
2 is sent to the video RAM control circuit 8 and the CR7 display output circuit 9 (see FIG. 3), and the display of the gear cradle to be displayed starts. Then, when the row display completion signal 21 given from the timing generator 4 (see FIG. 3) is input to the vertical direction display start signal generation circuit 17, the output of the vertical direction display start signal 22 is stopped, and the display row starts. , completes the display of the character.

Subsequently, the line number data 2o is changed to data indicating the second display line L2, and the vertical display start position data VQ of the display line L2 is sent to the data comparator 16, so that the output value of the counting circuit 15 is vertical display start position data VQ
, a match signal 24 is generated, and the vertical display start signal generation circuit 17 starts outputting the vertical display start signal 22, and this vertical display start signal 22 is transmitted to the bidet,
t RA M'#ArB@B8 The signal is sent to the Oyohi CRT display output diagram m9 (see 3rd M), and the display of the characters on the display line Lt begins. And timing generator 4
When the line display completion signal 21 given from (see FIG. 3) is input to the vertical direction display start signal generation circuit 17, the output of the vertical direction display start signal 22 is stopped, and the display of the character in the display line is stopped. Complete. After that, line number data 20
are changed sequentially, and each display line L3~ of the 3rd line to the Nth line
LH characters are sequentially vertically displayed starting position data V
Q.

~■Display is performed from the position corresponding to QN.

The above operations are repeated for each frame, and the video R
If the contents of AM7 are not changed, the same character will be displayed on the screen P over a plurality of frames.

In addition, by changing the vertical display start position data P in the first row of the register 19 for each frame, it is possible to prevent vertical scrolling of the character display on the screen or change the line spacing. You can move the characters on each line equally vertically with .

It is assumed that data transfer from the control microcomputer 2 to the vertical direction display start position control circuit 6B via the interface 3 has been completed in advance.

As described above, when the vertical synchronization signal 14 is input to the CR7 display circuit 1 in FIG. A signal 22 is output.

As described above, the vertical display start signal 22 generated for each display row L1''LN starts the operation of the CR7 display output circuit 9 and the VRAM control circuit 8 (see FIG. 3), and CLOCK 12. The display character code stored in the video RAM 7 accesses the character ROM 10 in accordance with the timing signal generated by the timing generator 4 according to the horizontal synchronization signal 13 and the vertical synchronization signal 14.

The output of the character ROM10 is converted into time series data synchronized with the horizontal synchronizing signal 13 by the shift register 11 and inputted to the CR7 display output circuit 9. The CR7 display output circuit 9 outputs a vertical synchronizing signal 14 and a horizontal synchronizing signal 13.
Outputs a CRT display signal synchronized with C, RT
The data will be supplied to a display device and characters will be displayed on the screen.

In the above embodiment, the counting circuit 15 is reset by the row display completion signal 21, so that the lower end of the previous display row is used as the starting point for determining the vertical display position of the display row. However, a signal generated at a certain position, for example, the top edge of the previous display line is created, and this signal is used to control the counting circuit 15.
If the configuration is such that the display line is reset, the top end of the previous display line can be used as the starting point. That is, the starting point for determining the vertical display position of each display line may be a certain degree W with respect to the previous display line.

〔Effect of the invention〕

According to the CRT display circuit of the present invention, all display lines on the screen can be moved equally by simply changing the vertical direction display start position data of the first display line on the screen, and It is possible to significantly reduce the large amount of data transfer that is a problem when it is necessary to change the vertical display start position of all display lines equally, such as when performing directional scrolling. When the vertical display start positions of all display lines are uniformly changed as in the case of vertical scrolling, the burden on the control microcomputer when rewriting vertical display start position data can be significantly reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a vertical display start position control circuit in a CRT display circuit according to an embodiment of the present invention;
Figure 2 is a conceptual diagram showing the concept of vertical display start position data on the screen in the configuration of Figure 1, and Figure 3 is a conceptual diagram of the conventional C
A block diagram showing the configuration of the RT display circuit, FIG.
5 is a block diagram showing the configuration of the vertical display start position control circuit in the CRT display circuit shown in FIG. 5. FIG. 5 shows the concept of vertical display start position data of the conventional vertical display start position control circuit on the screen. It is a conceptual diagram. DESCRIPTION OF SYMBOLS 1... CRT display circuit, 2... Control microcomputer, 3... Interface, 4... Timing generator, 5... Horizontal direction display start position control circuit,
6B... Vertical direction display start position control circuit, 7... Video RAM, 8... Video RAM control circuit, 9...
CRT display output circuit, IO...Character ROM,
11...Shift register, 12...Dot clock, 13...Horizontal synchronization signal, 14...Vertical synchronization signal,
15... Counting circuit, 16... Data comparator, 17.
...Vertical direction display start signal generation circuit, 18...Multiplexer, 19...Register, 20...Line number data, 21...Line display completion signal, 22...Vertical direction display start signal, 23 ...OR circuit, 24...-defeat signal, 25...CRT display signal diagram

Claims (1)

[Claims] Vertical display start position data of the first display line on the screen corresponds to the number of pulses of a horizontal synchronization signal from the vertical synchronization signal as a starting point to the vertical display start position of the first display line. The value is memorized, and the horizontal synchronization signal is used as the vertical display start position data for each display line from the second line onwards, starting from a certain position in the previous display line and ending at the vertical display start position of the relevant display line. a register storing a value corresponding to the number of pulses; a counting circuit that is reset at each starting point and counts the number of pulses of the horizontal synchronizing signal; and an output value of the counting circuit and the corresponding display line stored in the register. a data comparator that compares data with corresponding vertical display start position data; and a vertical display start signal generation circuit that generates a vertical display start signal for the display row in response to generation of a match signal from the data comparator. A CRT display circuit comprising a vertical display start position control circuit.