JPH0558199B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a window display control circuit for a display device used in an information processing device such as a personal computer.

[Prior art and its problems] In a CRT display device used in a personal computer for business use, the display screen is divided into a plurality of rectangular areas specified by arbitrary two-dimensional coordinates, and each area is The so-called multi-view port (multi-
viewport) method is used. In the windowing process to realize this multi-view port, when each window has a function to frame it, conventionally, the process of framing the window frame is done in the same way as window processing.
This was achieved using specific software under the control of the CPU. Furthermore, conventionally, when moving or changing a window, the contents (image data) of the display memory had to be rewritten each time.

Therefore, in the past, when trying to add window processing functions to a CRT display in order to realize a multi-view port, the software required for this processing became extremely complex, and this required control of the entire system. This makes the process more complex and puts a very heavy burden on the CPU.In addition, it is necessary to rewrite the image data in the display memory each time a window is moved or changed, which takes a lot of processing time and slows down the process. However, the disadvantage is that the processing speed is slow.

[Object of the Invention] The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to provide a window display control circuit that makes it possible to move and change windows using simple hardware without rewriting the display memory. With the goal.

[Summary of the Invention] The present invention is a window display control circuit that displays a plurality of windows on a display screen, and in which a horizontal pointer indicating a window display position for each predetermined dot unit in the horizontal direction corresponding to the display screen is moved to the plurality of windows. horizontal pointer storage means for storing a horizontal pointer corresponding to each window in the window; means for reading out the horizontal pointer corresponding to each window stored in the horizontal pointer storage means in synchronization with a predetermined dot scan in the horizontal direction; and a display screen. vertical pointer storage means for storing a vertical pointer indicating a window display position for each predetermined raster unit in the vertical direction corresponding to each of the plurality of windows; means for reading out the corresponding vertical pointer in synchronization with a predetermined raster scan, and a priority information storage for storing a plurality of priority information specifying an order in which each window is stacked when displaying the plurality of windows on a display screen. means for specifying one piece of priority information from among a plurality of pieces of priority information stored in the priority information storage means; contents of the horizontal pointer read from the horizontal pointer storage means and the vertical pointer; means for setting information indicating a window display period for each window based on the contents of the vertical pointer read from the storage means; and the setting contents of this means and the priority information storage means specified by the specifying means. A means for generating a display address for accessing predetermined window display data based on priority information is provided, and multiple windows can be displayed on a display screen using simple hardware without rewriting the display memory. The configuration allows display in an overlapping order based on a designated priority order, and allows windows to be moved and changed.

[Example] An example of the present invention will be described below with reference to the drawings. Here, up to four windows W0, W
1, W2, and W3 can be displayed overlapping or separately, one character is displayed as 16 x 16 dots, and screen rewriting (CPU window RAM access) is performed using the vertical blanking period. shall be.

FIG. 1 is a block diagram showing the configuration of essential parts in an embodiment of the present invention.

In the figure, 1 is connected to the CPU via data bus 2 and address bus 3, and is controlled by the CRT.
This is a CRT control unit that controls the display of the display unit.
From this CRT control unit 1, for screen scanning,
Horizontal synchronization signal (HSYNC), vertical synchronization signal (VSYNC), basic clock (dot clock)
CLOCK), character clock (CCLK), and display address (CA) for screen scanning.

4 receives various display control data for window display from the CPU via the data bus 2, and also receives horizontal synchronization signal (HSYNC), character clock (CCLK), display address (CA), etc. from the CRT control unit 1. In response to this, the window control unit outputs a converted display address (CCA) for window display and a fixed screen on/off control signal (su). The specific configuration of this window control section 4 is shown in FIG. 2, and the details will be described later.

Reference numeral 5 denotes a window RAM in which display image data is stored, and here it has a storage area for four screens, of which a predetermined area for one screen is used as a fixed screen (background screen) area, and each of these areas is You can specify screen areas for up to four windows.

6 via data bus 2 and address bus 3
A window connected to the CPU and under the control of the CPU
This is a RAM control unit that performs read/write control of the RAM5. From this RAM control unit 6, the CPU
Address selection control signal (AS) for selecting the CPU address (CPU-A) when accessing RAM and selecting the display address (CCA) when refreshing the display, and writing during the vertical retrace period according to write instructions from the CPU. A read/write control signal (R/W) that specifies the mode and the read mode during display access, a load signal (LO) for capturing the output (read) data of the window RAM 5, etc. are selectively output. be done.

7 selects the display address (CCA) or the CPU according to the address selection control signal (AS) from the RAM control unit 6.
Select the address (CPU-A) and open the window
This is an address selector that supplies RAM5.

8 is the load signal (LO) from the RAM control unit 6
This is a display data buffer that stores display data read out from the window RAM 5 according to the window RAM 5.

Reference numeral 9 denotes a latch circuit that latches the output data of the display data buffer 8, that is, image data in units of 16 bits here, and latches it when the fixed screen on/off control signal (su) is in the "0" state indicating off. It is released and outputs all "0" image data.

Reference numeral 10 denotes a parallel-to-serial converter circuit that sequentially converts the 16-bit width display data (image data) output from the latch circuit 9 into serial data according to the dot clock (CLOCK) generated by the CRT control unit 1 and outputs it as a video signal. .

Reference numeral 11 denotes a bus control unit that controls the transfer of display data (image data) between the data bus 2 and the window RAM 5.

FIG. 2 is a block diagram showing the internal structure of the window control section 4 described above.

In the figure, numeral 21 is a counter that receives a character clock (CCLK) generated by the CRT control section 1 and counts characters (0 to 47 in this case) in units of rows in synchronization with display scanning. 22 is
This is an address selector that selects either the count output of the counter 21 or the pointer address (6 bits) on the data bus 2 specified by the CPU in accordance with the write command (WE _H ) from the CPU. CPU on data bus 2 when (WE _H ) indicates write mode.
Select the specified address. 23 is window position specification data for specifying the start and end positions (digit positions) in the horizontal direction (horizontal direction) of each of the four windows W0, W1, W2, W3, that is, each of the four windows W0, W1, W2, Stores horizontal pointer information that specifies the horizontal frame position in character digit units for W3, and stores this horizontal pointer information in character digits (16 dots).
This is a horizontal pointer RAM that sequentially controls readout in synchronization with unit display scanning, and when a write command (WE _H ) from the CPU indicates write mode, it reads according to the specified address of the CPU output from the address selector 22. Horizontal pointer information sent from the CPU in 4-bit units HP0, HP1, HP2,
Memorize HP3 sequentially.

24 is horizontal pointer information HP0, HP1, 4 bits output from the horizontal pointer RAM 23.
This is a flip-flop circuit that holds HP2 and HP3. Horizontal pointer information HP0, HP1, HP2, stored in this flip-flop circuit 24,
Output the pointer corresponding to HP0 out of HP3.
The pointer output corresponding to HO0 and HP1 is set to HO1,
The pointer output corresponding to HP2 is expressed as HO2, and the pointer output corresponding to HP3 is expressed as HO3.

A counter 25 receives a horizontal synchronizing signal (HSYNC) generated by the CRT control section 1 and performs a raster (slice line) count (here, 0 to 511) in units of fields in synchronization with display scanning. 26 is the count output of the above counter 25 or the CPU according to the write command (WE _V ) from the CPU.
This is an address selector that selects one of the pointer addresses (9 bits) on data bus 2 specified by the write command (WE _V ) from the CPU.
Selects the designated address of the CPU on data bus 2 when indicates the write mode. 27 is window position designation data for designating the vertical direction (vertical direction) start and end positions (raster positions) of each of the four windows W0, W1, W2, W3, that is, each of the four windows W0, W1, W2, Store vertical pointer information in units of vertical dots for W3,
A vertical pointer RAM that sequentially reads and controls this vertical pointer information in synchronization with line scanning.
When the write command (WE _V ) from the CPU indicates write mode, the vertical pointer information VP is sent out by the CPU in 4-bit units according to the specified address of the CPU output from the address selector 26.
0, VP1, VP2, and VP3 are stored sequentially. 28
are 4-bit vertical pointer information VP0, VP1, VP2, output from the vertical pointer RAM 27.
This is a flip-flop circuit that holds VP3.
Among the vertical pointer information VP0, VP1, VP2, VP3 stored in this flip-flop circuit 28, the pointer output corresponding to VP0 is set to VO0, VP.
The pointer output corresponding to 1 is expressed as VO1, the pointer output corresponding to VP2 is expressed as VO2, and the pointer output corresponding to VP3 is expressed as VO3.

29 ₀ is the first of the 4-bit horizontal pointer information stored in the flip-flop circuit 24.
A pair of pointer outputs HO indicating the start position and end position in character digit units for window W0 of
a latch circuit which receives 0 and outputs "1" over a period from the rise of the signal indicating the start position to the rise of the signal indicating the end position _;
receives the pair of pointer outputs HO1 indicating the start position and end position in character digit units for the second window W1, and calculates the output in the period from the rise of the signal indicating the start position to the rise of the signal indicating the end position. The latch circuit ₂₉₂ , which is always in the "1" output state, receives the pair of pointer outputs HO2 indicating the start position and end position in character digit units for the third window W2, and outputs a signal indicating the start position. A latch circuit 293 outputs "1" from the rising edge to the rising edge of the signal indicating the end position. Reference numeral ₂₉₃ denotes a pair of latch circuits indicating the start position and end position of the fourth window W3 in units of character digits. The latch circuit receives the pointer output HO3 and outputs "1" during the period from the rise of the signal indicating the start position to the rise of the signal indicating the end position. This latch circuit 29
Of each latch output from ₀ to ₂₉₃ , latch circuit 29
The latch output of latch circuit ₂₉₁ is connected to HL0, the latch output of latch circuit ₂₉₁ is connected to HL1, and the latch output of latch circuit ₂₉₂ is connected to
HL2 and the latch output of the latch circuit ₂₉₃ are represented by HL3.

Further, ₃₀₀ receives the pair of pointer outputs VO0 indicating the start position and end position of each vertical dot for the first window W0 among the vertical pointer information stored in the flip-flop circuit 28, and indicates the start position. A latch circuit ₃₀₁ outputs "1" during the period from the rise of the signal to the rise of the signal indicating the end position.
A pair of pointer outputs indicating a start position and an end position in vertical dot units for window W1 of
a latch circuit that receives VO1 and outputs "1" over a period from the rising edge of the signal indicating the starting position to the rising edge of the signal indicating the ending position;
₀₂ receives the pair of pointer outputs VO2 indicating the start position and end position of each vertical dot for the third window W2, and calculates the period from the rise of the signal indicating the start position to the rise of the signal indicating the end position. The latch circuit ₃₀₃ , which outputs "1" throughout the period, receives the pair of pointer outputs VO3 indicating the start position and end position of each vertical dot for the fourth window W3, and indicates the start position. This is a latch circuit that outputs "1" during the period from the rise of the signal to the rise of the signal indicating the end position. This latch circuit 30 ₀
Of each latch output of ~30 ₃ , the latch circuit 30 ₀
The latch output of latch circuit 301 is VL1, the latch output of latch circuit ₃₀₂ is VL0, and the latch output of latch circuit ₃₀₁ is VL1.
VL2 and the latch output of the latch circuit ₃₀₃ are represented by VL3.

Here, when the outputs of the latch circuits 30 ₀ - 30 ₃ of the corresponding windows W0, W1, W2, W3 are "0", the latch circuits 29 ₀ - 29 ₃ clear the latch contents "1" → When the contents of the corresponding bits of the screen on/off designation register 31, which will be described later, are "0", the latch contents of the latch circuits ₃₀₀ to ₃₀₃ are similarly cleared.

31 is a screen on/off designation register that stores screen on/off designation information for the fixed screen and each window sent from the CPU via the data bus 2 during the vertical retrace period; LA) stores 5-bit screen on/off designation information on data bus 2. Of the 5-bit screen on/off designation information, bit S0 is for window W0, bit S1 is for window W1, and bit S2 is for window W1. Window W2, bit S3 is window W3, bit S4
corresponds to a fixed screen, and when each bit output is "0", it indicates erasure of the corresponding screen.

32 is a priority register that stores window priority designation information sent from the CPU via the data bus 2 during the vertical retrace period;
According to the load timing signal (LB) from the CPU, 5-bit priority designation information that designates the superimposition order (24 ways in total) of the four windows W0, W1, W2, and W3 is stored.

Reference numerals 33 denote the latch outputs HL0, HL1, HL2, HL3 of the latch circuits ₂₉₀ to ₂₉₃ , and the bit outputs S4 to S4 of the priority register 32, respectively.
This is a priority ROM that takes S0 as input data (read address) and outputs 3-bit priority control information P1, P2, and P3 for window display control specific to the input data. Here, among the priority control information P1, P2, and P3, P3
is the display specification bit for [fixed screen/window], P2 and P1 are the window selection specification bits, and when P0="1", fixed screen display, P
0="0" indicates window display, P2, P1
= “0”, window W0, P2 = “0”, P1 =
If “1”, window W1, P2 = “1”, P1 =
"0" indicates windows W2, P2, and P1="1" indicates window W3.

34 is an offset register that latches the offset RAM specified address sent from the CPU via the data bus 2 and a part of the offset address stored in the specified area during the vertical retrace period; In accordance with the load timing signal (LC), 2-bit address data for storing the offset address for each window in the offset RAM 36, which will be described later, is transferred to bit S.
15, S14, and a part (here, the upper 2 bits) of the offset address (18 bits) stored in that area is stored in bits S1, S0.

35 follows the write command (WE ₀ ) from the CPU,
When writing the offset address, the 2-bit data stored in bits S15 and S14 of the offset register 34 is written to the offset RAM 36.
This is an address selector that selects the 2-bit data of P1 and P2 of the priority control information P1, P2, and P3 outputted from the priority ROM 33 as the address of the offset RAM 36 during display operation. be.

36 indicates each window W0, W sent out from the CPU via the data bus 2 during the vertical retrace period.
1, W2, and W3, and store output data P1, P2 of the priority ROM 33 during display operation.
Offset to read offset address according to
RAM, and according to the write command (WE ₀ ) from the CPU, bits S15 of the offset register 34,
In the address area specified by the 2-bit address data stored in S14, the upper 2-bit offset address also stored in bits S1 and S0 of the offset register 34 and the data bus 2 are stored.
Stores the remaining 16-bit offset address above.

37 is an AND circuit that selectively inhibits the output data of the offset RAM 36, that is, the offset address, according to the contents of the output bit P3 of the priority ROM 33;
When the output bit P3 of the ROM 33 is "1" indicating a fixed screen display, the output ("0") of the inverter 39 prohibits input of the offset address to the adder circuit 38, which will be described later.

38 adds an offset address selectively outputted via the AND circuit 37 to the display address (CA) outputted from the CRT control unit 1;
This is an adder circuit that obtains the display address (CCA) of the window RAM 5.

40 is the bit output P3 of the priority ROM 33 and the screen-on signal inverted by the inverter 41.
This is a NAND circuit that receives the bit output S4 of the off designation register 31 and outputs a fixed screen on/off control signal (su).

FIG. 3 shows the latch circuits 29 ₀ to 29 shown in FIG. 2 above.
₂₉₃ is a circuit block diagram showing the internal circuit configuration of the latch circuit ₃₀₀ to ₃₀₃ shown in FIG. 2 above.
It is a circuit block diagram showing the internal circuit configuration of D.
It can be easily realized using type flip-flops FF1, FF4, delayed flip-flops, etc. as main components.

Figure 5 shows the horizontal pointer RAM shown in Figure 2 above.
FIG. 6 is a time chart showing the signal timing of each part according to the data. Further, FIG. 7 shows an example of data storage in the vertical pointer RAM 27 shown in FIG. 2, and FIG. 5 is a time chart showing signal timings of various parts according to the data. Note that the signal states of each part in FIG. 6 are shown using the raster timing of the 502nd raster in FIGS. 7 and 8 as an example. Therefore, at the above raster timing, the latch circuit 3
Since the latch output VL0 of ₀₀ has already become "0", the latch output HL0 of the latch circuit ₂₉₀ is forcibly returned to "0".

Figure 9 shows the priority ROM3 shown in Figure 2.
3 is a diagram showing the correspondence between addresses A8 to A0 of No. 3 and output data (priority control information: P1, P2, P3). FIG.

Figure 10 shows the window RAM shown in Figure 1 above.
This is a map that includes the screen area of the specified window in 5. Here, the storage area for 4 screens is shown.
Has PA, PB, PC, PD, of which one predetermined screen area PA is fixed screen (background screen)
As areas, screen areas M0, M1, M2, and M3 for up to four windows W0, W1, W2, and W3 can be specified in each of these areas. still,
In the figure, m0, m1, m2, and m3 indicate the start address of each window area, and n0 to n3 indicate the start address of each window area when the windows are overlapped in the fixed screen area PA. Therefore, here, m0-n0 is the offset address OF0, m1-n0 of window W0.
n1 is the offset address OF of window W1
1, m2-n2 is the offset address OF2 of the window W2, and m3-n3 is the offset address OF3 of the window W3.

Figure 11 shows the offset RAM shown in Figure 2 above.
36 2-bit address input (A0, A1=P
1, P2 (or S1 of offset register 34
5, S14)) and offset address OF0~OF
3 is a diagram showing the correspondence with No. 3.

Figure 12 shows each of the above windows W0, W1, W.
2. It is a figure which shows the display state (view port) of W3.

Here, the operation of one embodiment will be explained with reference to FIGS. 1 to 12.

During normal display operation, the CRT control unit 1:
The display of the CRT display section is controlled under the control of the CPU, and the fixed screen stored in the fixed screen area PA of the window RAM 5 or the view port screen specified by the window of the window control section 4 is displayed on the CRT. At this time, the CPU selectively updates and sets various information, such as updating the display image and setting multi-windows, during the vertical retrace period. That is, when rewriting image data, the CPU sends a data write command to the RAM control unit 6 via the data bus 2 during the vertical retrace period, and then sends the CPU address (CPU-A) onto the address bus 3. ) and sends the image data to be written onto the data bus 2.
In accordance with the data write command received from the CPU, the RAM control unit 6 outputs an address selection control signal (AS) and a read/write control signal (R/W) according to the contents of the command.
W) etc., and set the address selector 7 to the CPU.
Set the address selection mode to window RAM 5.
into write mode. This will cause the window
The CPU address on the address bus 3 is given to the RAM 5 as a write address via the address selector 7, and the image data on the data bus 2 is given as write data via the bus control unit 11. Data is updated.

Further, when setting various information for window display in the window control unit 4, the CPU selects various information to be set and its setting control signal via the data bus 2 during the vertical retrace period. The window controller 4 is set accordingly. Specifically, the screen on/off designation information is set in the screen on/off designation register 31 using the load timing signal (LA), and the screen on/off designation information is set in the screen on/off designation register 31 using the load timing signal (LB).
The window priority designation information is set in the priority register 32, and the load timing signal (LC) is used to set the 2-bit offset RAM designated address and a portion (2 bits) of the offset address (18 bits) stored in that designated area. ) is set in the offset register 34.

Also, various windows W to the offset RAM 36
When setting the offset addresses of 0, W1, W2, and W3, the load timing signal (LC) is used to set the 2-bit offset RAM specified address,
After setting a part (2 bits) of the offset address (18 bits) stored in the specified area in the offset register 34, the remaining offset address (16 bits) to be written on the data bus 2 is set. A write command (WE ₀ ) is sent to the address selector 35 and the offset RAM 36, respectively, and each window W0, W1, W2, Screen area M for W3
18-bit offset address OF0, OF1, OF2, for specifying 0, M1, M2, M3.
Write OF3.

Furthermore, the write command (WE _H ) causes the horizontal pointer RAM 23 to read, for example, as shown in FIG.
Horizontal pointer information for specifying the horizontal start and end positions (digit positions) of each window W0, W1, W2, and W3 is set, and the vertical pointer RAM 27 is set by a write command (WE _V ).
For example, each window W as shown in FIG.
Vertical pointer information for specifying the vertical direction (vertical direction) start and end positions (raster position; vertical dot position) of 0, W1, W2, and W3 is set.

In this way, under the control of the CPU, the display image on the window RAM 5 is updated, window information is set, etc. during the vertical retrace period.

During the display operation (during display refresh) after setting the various window information described above, the display window control unit 4 sets the offset addresses OF0,
The display address (CCA) converted based on OF1, OF2, and OF3 is output, the window RAM 5 is read and controlled by the address (CCA), and the display data (image data) read from the window RAM 5 is displayed. The signal is inputted to a parallel-to-serial conversion circuit 10 via a data buffer 8 and a latch circuit 9, where it is converted into serial data and then sent to a CRT display unit (not shown) as a video signal.

Here, the display operation of the window and the window frame will be explained with reference to FIGS. 2 to 12.
In the window RAM 5, the counter 21 is
Based on the character clock (CCLK) from the CRT control section 1, a character count (0 to 47) is performed in units of rows in synchronization with display scanning. The count output of this counter 21 is
The horizontal pointer RAM 23 is used as an address for reading horizontal pointer information for specifying the horizontal direction (horizontal direction) start and end positions (digit positions) of 0, W1, W2, and W3 through the address selector 22.
supplied to This allows horizontal pointer RAM
From 23 onwards, as shown in Figs. 5 and 6, the horizontal data is synchronized with the character clock (CCLK) in units of 4 bits, with bit correspondence taken in each window W0, W1, W2, and W3. pointer information
HP0, HP1, HP2, HP3 are read out sequentially,
Each time, it is held in the flip-flop circuit 24.

On the other hand, the counter 25 uses a raster count (from 0 to
511) Do. The count output of the counter 25 is supplied to the vertical pointer RAM 27 via the address selector 26 as an address for reading vertical pointer information for specifying the vertical direction (vertical direction) start and end positions (raster positions) of the window. Ru. As a result, bit correspondence is established from the vertical pointer RAM 27 to each window W0, W1, W2, and W3 in synchronization with the horizontal synchronization signal (HSYNC), that is, raster scanning, as shown in FIGS. 7 and 8. Vertical pointer information VP0, VP1, VP2, and VP3 in units of 4 bits are read out sequentially.
Each time, it is held in the flip-flop circuit 28.

The pointer outputs HO0, HO1, HO2, and output HO3 of the flip-flop circuit 24 are as follows:
The pointer outputs VO0 and VO of the flip-flop circuit 28 are supplied to the latch circuits _{29 0} to 29 ₃ .
1, VO2, and VO3 are supplied to latch circuits 30 ₀ to 30 ₃ .

The latch circuits 29 ₀ to 29 ₃ connect the corresponding pointers HO0, HO1, HO1,
Receives HO2 and HO3, latch circuit 30 ₀ ~ 30 ₃
receive the corresponding pointer outputs VO0, VO1, VO2, and VO3 of the flip-flop circuit 28, and as shown in FIGS. 6 and 8, respectively, from the first rising edge of the input signal to the next rising edge, Latch signals HL0 and HL at “1” level
1, HL2, HL3, VL0, VL1, VL2, VL
Outputs 3.

At this time, the latch circuits 30 ₀ to 30 ₃ receive the corresponding bit outputs S0 to S3 of the screen on/off specification register 31, and the corresponding bit outputs are "0", indicating erasure of the screen. At this time, the latch is forcibly released (direct reset) and its output becomes "0". Furthermore, the latch circuit 29 ₀
~29 ₃ are the corresponding latch circuits 30 ₀ ~30
When _{the three} latch outputs VL0, VL1, VL2, and VL3 are respectively received and the corresponding latch output is "0", the latch is forcibly released (direct reset) and its output becomes "0". The specific circuit configuration of the latch circuits 29 ₀ to 29 ₃ is as follows.
The specific circuit configuration of the latch circuits 30 ₀ to 30 ₃ is shown in FIG.

As a result, from the latch circuits 29 ₀ to 29 ₃ ,
Only at the timing when a pre-specified window area is scanned, the latch outputs HL0, HL1, HL2, and HL3 corresponding to that window selectively become "1" level.

The latch outputs HL0, HL1, HL2, and HL3 of the latch circuits 29 ₀ to 29 ₃ are used as priority outputs along with the 5-bit priority designation information stored in the priority register 32 described above.
It is supplied to the ROM 33 and becomes the read address of the ROM.

The priority ROM 33 is the latch circuit 2 mentioned above.
9 ₀ to 29 ₃ latch outputs to lower addresses A0 to A
3, and the output of the priority register 32 (priority designation information) is set to upper addresses A8 to A4.
According to the address, 3-bit priority control information P1, P2, P3 is output. FIG. 9 shows the relationship between the input address of the priority ROM 33 and the output data, that is, the priority control information P1, P2, and P3 at this time. Incidentally, FIG. 9 shows an input/output example when the upper input addresses A8 to A4, that is, the priority order designation information output from the priority register 32 are all "0". , here, the window W0,
The specified order of W1, W2, and W3 is [W1>W2>W
3>W0].

Among the priority control information P1, P2, and P3 output from the priority ROM 33, P3 is a display designation bit for [fixed screen/window], P2 and P1 are window selection designation bits, and P0= Fixed screen display with “1”, P0
= “0” indicates window display, P2, P1 =
If “0”, window W0, P2 = “0”, P1 =
If “1”, window W1, P2 = “1”, P1 =
"0" indicates windows W2, P2, and P1="1" indicates window W3.

Bit output P of the priority ROM 33 above
1, P2 are supplied to the offset RAM 36 via the address selector 35, and the bit output P2 is supplied to the offset RAM 36 via the address selector 35.
3 is supplied to the AND circuit 37 via the inverter 39, and is also supplied to the bit output S4 of the screen on/off designation register 31 via the inverter 41.
It is also supplied to the NAND circuit 40.

The offset RAM 36 above has a priority
Priority control information P1 output from ROM33,
When bit outputs P1 and P2 of P2 and P3 are input as read addresses through the address selector 35, the stored windows W0 and W
1, W2, W3 offset address OF0, OF
Outputs the offset address (OFi; 18 bits) of one window unique to the input address from among 1, OF2, and OF3. This offset
Offset address read from RAM36
OFi is supplied to an adder circuit 38 via an AND circuit 37.

At this time, the bit output P3 of the priority ROM 33 is "1" indicating the fixed screen display mode.
When , the output of the offset address is prohibited by the AND circuit 37 due to the inverted output of the inverter 39 being "0".

When the above bit output P3 is “0” indicating window display mode, the offset
The offset address read from the RAM 36 is supplied to the adder circuit 38 via the AND circuit 37, and this offset address is added to the display address (CA) output from the CRT control section 1.
The adder circuit 38 outputs a display address (CCA) that has undergone address conversion processing for window display. This display address (CCA) is supplied to the window RAM 5 via the address selector 7, and reading from the window RAM 5 is controlled according to this display address (CCA).

As a result, the image data in the window designated area with the highest priority is always read out from the window RAM 5 in the stacking order of the windows according to the set priority order, and this image data is input to the display data buffer 8.

The image data in units of 16 bits stored in the display data buffer 8 is supplied to a parallel-to-serial conversion circuit 10 via a latch circuit 9.

At this time, the latch circuit 9
If the fixed screen on/off control signal (su) inputted from above indicates "0", all latch outputs at that time are set to "0" and the corresponding screen (fixed screen) is erased. That is, priority ROM3
When the bit output P3 of 3 is "1" indicating display of a fixed screen, and the bit output S4 of the screen on/off designation register 31 is "0" indicating erasure of the fixed screen, the NAND circuit is activated. 40 outputs a fixed screen on/off control signal (su) of "0" level. As a result, the latch circuit 9 sets all its display output data to "0" at the fixed screen display data output timing, and selectively erases only the display data in the fixed screen area.

The parallel-to-serial converter circuit 10 converts the image data received from the latch circuit 9 into the CRT controller 1.
The data is sequentially converted into serial data in synchronization with the dot clock (CLOCK) output from the video signal, and sent as a video signal to a CRT control unit (not shown).

As described above, the overlapping display process of a plurality of windows is executed under hardware control.

Therefore, multiple windows can be displayed using relatively simple hardware without placing a burden on the CPU.

In the above-mentioned embodiment, the number of windows that can be superimposed is four, but the number is not limited to this, and any number of window display functions can be provided. Further, in the above-described embodiment, the operation has been described as a configuration in which image data and window control information are set during the vertical retrace period, but the operation is not limited to this. For example, image data reading and writing are performed. Even in an image memory access method in which (updating) is performed alternately in half cycles, the window and window frame display control mechanism according to the above embodiment can be easily realized. Moreover, in the above-mentioned lower embodiment,
Although the RAMs 23 and 27 are used as storage means for the horizontal pointer and vertical pointer for window designation, the present invention is not limited to this. For example, a shift register may be used for each of the above storage means and shift control may be performed in synchronization with display scanning. It may also be a configuration.

[Effects of the Invention] As detailed above, according to the window display control circuit of the present invention, multiple windows can be displayed on the display screen with specified priority using simple hardware without rewriting the display memory. Windows can be displayed in a superimposed order based on ranking, and windows can be moved and changed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention;
FIG. 2 shows the window control section 4 in the above embodiment.
3 is a circuit block diagram showing the structure of the latch circuits 29 ₀ to 29 ₃ in FIG. 2, and FIG. 4 is a circuit block diagram showing the structure of the latch circuits 30 ₀ to 30 in FIG. 2. _3. FIG. 5 is a diagram showing an example of data storage in the horizontal pointer RAM 23 in FIG. 2. FIG. 7 is a diagram showing an example of data storage in the vertical pointer RAM 27 in FIG. , Fig. 6, and Fig. 8 are time charts showing the signal timing of each part in Fig. 2 above, and Fig. 9 shows the priority in Fig. 2 above.
A diagram showing an input/output example of the ROM 33, FIG. 10 is a diagram showing a map including the window designated area of the window RAM 5 in FIG. 1 above, and FIG. 11 is a diagram showing the address data storage of the offset RAM 36 in FIG. 2 above. FIG. 12 is a diagram showing an example of a window display. 1...CRT control unit, 2...data bus, 3...
...Address bus, 4...Window control section, 5...
...Window RAM, 6...RAM control section, 7...
... Address selector, 8 ... Display data buffer, 9 ... Latch circuit, 10 ... Parallel-serial conversion circuit, 11 ... Bus control section, 21 ... Counter, 22 ... Address selector, 23 ... Horizontal pointer RAM, 24...Flip-flop circuit, 25...Counter, 26...Address selector, 27...Vertical pointer RAM, 28...Flip-flop circuit, ₂₉₀ to ₂₉₃ ...Latch circuit, ₃₀₀ to ₃₀₃ ...Latch circuit, 31...Screen on/off designation register, 32...Priority register, 33...Priority ROM, 3
4...offset register, 35...address selector, 36...offset RAM, 37...AND circuit, 38...addition circuit, 39...inverter, 40...NAND circuit, 41...inverter,
W0 to W3...Window, OF0 to OF3...Offset address, priority control information, P1, P
2, P3...Priority control information.

Claims (1)

[Scope of Claims] 1. A window display control circuit that displays a plurality of windows on a display screen, wherein a horizontal pointer indicating a window display position for each predetermined dot unit in the horizontal direction corresponding to the display screen is displayed on the plurality of windows. horizontal pointer storage means for storing a horizontal pointer corresponding to each window; means for reading out the horizontal pointer corresponding to each window stored in the horizontal pointer storage means in synchronization with a predetermined dot scan in the horizontal direction; vertical pointer storage means for storing a vertical pointer indicating a window display position for each predetermined raster unit in the vertical direction corresponding to each window in the plurality of windows; means for reading out the vertical pointer in synchronization with a predetermined raster scan; and priority information storage means for storing a plurality of pieces of priority information specifying an order in which each window is stacked when displaying the plurality of windows on a display screen. , specifying means for specifying one piece of priority information from a plurality of pieces of priority information stored in the priority information storage means, and the contents of the horizontal pointer read from the horizontal pointer storage means and the vertical pointer storage means. Based on the contents of the vertical pointer read from
means for setting information indicating a window display period for each window; and accessing predetermined window display data based on the settings of this means and the priority information in the priority information storage means designated by the designation means. 1. A window display control circuit comprising: means for generating a display address for a window display control circuit.