JPH05101203A - Microprocessor - Google Patents

Abstract

PURPOSE:To recover the miswriting operations of a built-in I/O access address holding register. CONSTITUTION:The registers 10a and 10b are provided to hold the addresses where the accesses are given to the built-in peripheral devices (I/O) 14a end 14b respectively together with the comparators 5a and 5b which compare the addresses outputted with the accesses given to the I/O 14a and 14b with the outputs of the registers 10a and 10b and then output the built-in I/O access signals 20 when the coincidence is secured through the comparison, the rewrite inhibition flags 9a and 9b which inhibit the rewrite to the registers 10a and 10b, and an interruption signal generating circuit 16 which produces an interruption request signal 12 when the built-in I/O accesses are carried out in the inhibition states of the flags 9a end 9b.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor, and more particularly to a microprocessor architecture having a peripheral (hereinafter referred to as I / O) in a chip and a decoder for accessing this I / O. Regarding

[0002]

2. Description of the Related Art Conventionally, in this type of microprocessor, a built-in I / O built in a chip as shown in FIG.
When accessing 14a, 14b, the built-in I / O selection address registers 10a, 10b have built-in I / O 14 in advance.
Addresses for accessing a and 14b are stored as shown in the state diagram of FIG. 4, and when the address comparison control signal 4 is received from the central processing unit 1, this address is compared with the address output from the address bus 2 when they match. Circuits 5a, 5
b to output the built-in I / O access signal 20 to output the I / O 14a,
14b is executed.

[0003]

However, in the above-described conventional microprocessor, it is defined in advance.
Since writing to the address register that stores the I / O address can be performed freely, for example, there is a case where an erroneous rewriting is inadvertently executed by an execution program on a general-purpose operating system. For this reason, there is a problem that an expected operation cannot be performed as a system by accessing an absent I / O address.

It is an object of the present invention to provide a microprocessor capable of recovering an erroneous write in an internal I / O access address holding register.

[0005]

A microprocessor of the present invention comprises an address register for holding an address signal for outputting an internal peripheral access signal,
When the control signal is input from the central processing unit and the address signal output from the address register is compared with the address signal output from the address bus when the internal peripheral is accessed, the internal peripheral is compared with the internal peripheral. -A comparator that outputs an access signal, a prohibition flag for rewriting the address register, and an interrupt request signal when the internal peripheral is accessed while the prohibition flag is in the prohibition state And an interrupt signal generation circuit for

[0006]

The present invention will be described below with reference to the drawings.
FIG. 1 is a block diagram of the first embodiment of the present invention. In the microprocessor of this embodiment, the built-in I / O 14a, 1
4b for accessing the built-in I / O selection address registers 10a, 10b and the address output from the address bus 2 at the time of I / O access by inputting the address comparison control signal 4 and the registers 10a, 10b. Comparators 5a and 5b that output the built-in I / O access signal 20 when the output signals are compared with each other, and registers 10a and 10b
And the interrupt signal generation circuit 16 for generating the interrupt request signal 12 when the internal I / O access is executed when the flags 9a and 9b are prohibited. Have

The microprocessor of this embodiment comprises a central processing unit 1, a 20-bit address bus 2, an 8-bit data bus 13 and two built-in I / Os 14a and 14b.
Have and. The decoding address 3 of the lower 8-bit address of the address bus is input to the write signal decoder 7. The address comparison control signal 4 output from the central processing unit 1 causes the comparators 5a and 5b to compare the contents of the built-in I / O selection address registers 10a and 10b with the I / O address output during instruction execution. If they match, the access signal 20 is output to the built-in I / Os 14a and 14b corresponding to this address. Address holding register common write signal 6 for accessing the built-in I / Os 14a and 14b
Are converted into register write signals 8a and 8b by the write signal decoder 7, and write inhibit flags 9a and 9b.
b and flag outputs 11a and 11b are interrupt signal generation circuits 1
If the address registers 10a and 10b are written to the address registers 10a and 10b when the flags 9a and 9b are set, the interrupt request signal 12 is enabled and the central processing unit 1 is interrupted.

In this embodiment, the flags 9a and 9b are cleared by an external reset signal 15 to the system, and the address registers 10a and 10 to be executed next are executed.
Only set by writing to b. This is a general R
/ S flip-flop. In the present embodiment, when an incorrect I / O access is made, the cause can be determined in the interrupt handler that generated it.

FIG. 2 shows a block diagram of the second embodiment of the present invention. The flag reset signal generation circuit 18 uses the flag access signal 1 in a specific interrupt handler routine.
7 and an external reset signal 15 are input to generate a flag reset signal 19 by a flag access signal in a specific interrupt handler routine.

In this embodiment, the reset of the prohibition flags 9a and 9b is added to the external reset signal to access the flag in a specific interrupt handler routine. The access signal to the flag in this particular interrupt handler routine can be distinguished from other I / O signals by holding the interrupt vector and the I / O access signal.

[0011]

As described above, in the microprocessor of the present invention, when an incorrect I / O access is made,
It is possible to determine the cause in the interrupt handler that generated it, and to correct it.
It is possible to prevent malfunctions and the like.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a block diagram of a second embodiment of the present invention.

FIG. 3 is a block diagram of an example of a conventional microprocessor.

FIG. 4 is a state diagram of a register shown to explain the operation of the block of FIG.

5A to 5E are state diagrams of registers shown for explaining the operation of the block of FIG. 3 respectively.

[Explanation of symbols]

 1 central processing unit 2 address bus 3 decoding address 4 address comparison control signal 5a, 5b comparator 6 address holding register 7 write signal decoder 8 register write signal 9a, 9b write inhibit flag 10a, 10b built-in I / O selection address・ Registers 11a, 11b Flag output signal 12 Interrupt request signal 13 Data bus 14a, 14b Built-in I / O 15 External reset signal 16 Interrupt signal generation circuit 17 Flag access signal 18 Flag reset signal generation circuit 19 Flag reset signal 20 Built-in I / O access signal

Claims (1)

[Claims] 1. An address register for holding an address signal for outputting a built-in peripheral access signal, and a control signal input from a central processing unit to access the address signal output from the address register and the built-in peripheral. At this time, the comparator outputs the built-in peripheral access signal when the address signals output from the address bus are compared with each other, a prohibit flag for rewriting the address register, and the prohibit flag. A microprocessor, comprising: an interrupt signal generation circuit that generates an interrupt request signal when the access to the built-in peripheral is executed while the flag is in a disabled state.