JPH05102772A - Nonlinear amplifier - Google Patents

Abstract

PURPOSE:To set clearly a knee point in an output voltage by providing a branching rectifier circuit connecting in series with one differential amplifier circuit of a differential amplifier. CONSTITUTION:The amplifier is provided with a differential amplifier 1 comprising NPN transistors(TRs) 2, 3, constant current sources 4, 5 and a resistor 6 relating to an input signal source 13, a branching rectifier path 7 comprising NPN TR 8, 9, a PNP TR10, and a constant voltage source 11, a constant current source 14 setting a knee point voltage, a constant voltage source 12 and a resistor 15 acting like a load resistor. Then a current flowing to the load resistor 15 is increased proportional to an input voltage in excess of the knee point voltage through the branching rectifier circuit 7 to decrease the apparent voltage gain and the knee point in an output voltage is clearly set.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-linear amplifier, and more particularly to a non-linear amplifier applied to a KNEE circuit used in a video signal processing circuit such as a video camera.

2. Description of the Related Art Generally, this type of non-linear amplifier is used as a knee circuit having a specific bent output characteristic with respect to an input voltage in a video signal processing circuit in a video camera or the like.

A conventional non-linear amplifier of this type has NPN transistors 17 and 18, a constant current source 19 corresponding to an input signal source 26, as shown in FIG.
And 20, and resistors 21 and 22, and a differential amplifier 16, a resistor 23, a diode 24, and constant voltage sources 25 and 26. Here, the constant voltage source 27 is a constant voltage source for setting a knee point (bending point voltage) corresponding to the input voltage in the linear amplifier. In addition, FIGS. 4A and 4B are diagrams showing operation characteristics in the conventional example.

In FIG. 3, resistors 21, 22 and 23 are shown.
And of the resistance value R _21, R ₂₂ and R _23, respectively, when the impedance of the diode 24 and R _D24, the output load resistance R _L is expressed by the following equation.

_RL = R ₂₁ − (R ₂₁ ) ² / (R ₂₁ + R ₂₃ + _{RD 24} ) ... (1) If the current flowing through the diode 24 is I _D24 , the impedance R _{D24 of the} diode 24 is given by the following equation. Is represented.

R _D24 = kT / qI _D24 (2) In the above formula (2), k is the Poltzmann constant, T is the absolute temperature, and q is the electron charge. is there.

Referring to FIG. 4B, the input voltage V _i of the input signal source 27 is in the level range of 0 ≦ V _i <V ₁ ,
In the case where the output voltage is at a low level state than V _o, the diode 24 is in a cutoff state. That is, I _D24 = 0
From the above equation (2), the impedance R _{D24 of the} diode 24 becomes infinite. So in this case,
From equation (1), R _L = R ₂₁ , and the voltage gain during this period is R ₂₁ / R ₂₂ .

Next, referring to FIG. 4B, the input voltage V
_{When i} is in the level range of V _i > V ₂ , the diode 24 is in the conductive state, and the current I _D24 is several hundred μ.
About A will flow. This allows the diode 24
Impedance R _D24 of, as evidenced by equation (2), the value of R _D24 is an extremely small value compared to the values of R ₂₁ and R _23. Therefore, the combined output load resistance can be approximately set to R _D24 = 0 in the above equation (1), and R _L = R ₂₁ · R ₂₃ / (R ₂₁ + R ₂₃ ). As the voltage gain, R _L / R ₂₂ = R
₂₁ · R ₂₃ / R ₂₂ (R ₂₁ + R ₂₃ ).

Next, referring to FIG. 4B, the input voltage V
_{When i} is in the level range of V ₁ <V _i ≦ V ₂ , the diode 24 is in the region where it changes from the cut-off state to the conduction state, and the impedance R _{D24 of the} diode 24 is R _21.
Since R ₂₃ and R ₂₃ have values that cannot be ignored, the combined output load resistance changes as shown in FIG. Therefore, the voltage gain R _L / R ₂₂ during this period gradually changes as shown in FIG. 4B, and the knee point (bending point) in the output voltage does not clearly appear.

In the conventional non-linear amplifier described above, as shown in FIG. 4A, the voltage gain is changed by changing the output load resistance to obtain a desired output waveform. The input voltage V _i is V
_In the level range of ₁ <V _i ≦ V ₂ , when the diode 24 shifts from the cut-off state to the conductive state, the impedance value of the diode 24 becomes a value that cannot be ignored in comparison with the load resistance. , Fig. 4
In the state where the input voltage V _{i in} (a) is close to the voltage V ₂ , the combined output load resistance during operation cannot change sharply but changes gradually. To this end, FIG.
As seen in (b), there is a drawback in that the knee point cannot be clearly set as the change in the output voltage.

[0009]

A non-linear amplifier according to the present invention includes first and second NPN transistors whose emitters are connected to each other by emitter resistors, corresponding to a predetermined input signal source. Differential amplifier formed by using the collector of the NPN transistor as an output terminal, a constant current source inserted and connected between the high-potential DC power supply and the collector of the first NPN transistor, the high-potential DC power supply, and the A load resistance connected in series with the output terminal,
The base is commonly connected to the positive side of a predetermined constant voltage source, the emitter is commonly connected to the collector of the first NPN transistor, and the collectors are individually connected to the high potential DC power supply and the output terminal, respectively. 3rd
And a fourth NPN transistor, a PNP having an emitter connected to the collector of the first NPN transistor, a base connected to the bases of the third and fourth NPN transistors, and a collector connected to a ground potential. And a transistor.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention. As shown in FIG. 1, this embodiment uses an input signal source 1
Corresponding to 3, a differential amplifier 1 formed by NPN transistors 2 and 3, constant current sources 4 and 5, and a resistor 6, NPN transistors 8 and 9, a PNP transistor 10 and a constant voltage source 11 are formed. The shunt rectifier circuit 7, a constant voltage source 12, a constant current source 14 that sets a knee point voltage, and a resistor 1 that functions as a load resistor.
And 5. The NPN transistor 8
And 9 form a shunt circuit, and the shunt ratio is set by making the emitter area ratio of both NPN transistors appropriate. Further, FIGS. 2A and 2B are diagrams showing the operating characteristics in the present embodiment,
2A shows the amount of change in the collector currents I ₃ and I ₉ of the NPN transistors 3 and 9 corresponding to the input voltage V _i , and FIG. 2B corresponds to the input voltage V _i . shows the output voltage V _o.

In FIG. 1, the resistance values of the resistors 6 and 15 are R ₆ and R ₁₅ , respectively, and the NPN transistor 2
_Let I _{c2 be} the collector current of the constant current sources 4, 5 and 14
2 (b), where I ₄ , I ₅ and I ₁₄ are the current values of
The input voltage V _i of the input signal source 13 is 0 ≦ V
_When the output voltage is lower than the knee point voltage V _{1 in} the level range of _i <V ₁ , the NPN transistor 2
The collector current I _{c2 of} is expressed by the following equation.

I _c2 = V _i / R ₆ + I ₄ (<I ₁₄ ) (3) Therefore, the difference current (I ₁₄ −I _c2 ) between I _c2 and I ₁₄ is PN.
It flows through the P-transistor 10. At this time, NP
Since N-transistors 8 and 9 are cut off, no current flows. Therefore, via the NPN transistor 3,
The output voltage V _o at the output terminal 51 is given by the following equation due to the current flowing through the resistor 15 forming the load resistance.

V _o = V _i (R ₁₅ / R ₆ ) (4) That is, the input voltage V _i is in the level range of 0 ≦ V _i <V _1. In some cases, the output voltage V _o changes in the form of (R ₁₅ / R ₆ ) as the constant of proportionality (see FIG. 2B).

Next, when the input voltage V _i is in the level range of V _i ≧ V ₁ and the output voltage is higher than the knee point voltage, the collector current I _c2 of the NPN transistor 2 is the same as described above. Similar to the equation (3), it is represented by the following equation.

I _c2 = V _i / R ₆ + I ₄ (≧ I ₁₄ ) (6) Therefore, the difference current (I _c2 −I ₁₄ ) between I _c2 and I ₁₄ is _calculated by the following equation. Is represented by

I _cd −I ₁₄ = (V _i / R ₆ + I ₄ ) − (V ₁ / R ₆ + I ₄ ) = (V _i −V ₁ ) / R ₆ (7) The difference current (I _cd −I ₁₃ ) will flow through the NPN transistors 8 and 9. Assuming that the value of n is smaller than 1 and the emitter size ratio of the NPN transistors 8 and 9 is n: (1-n), the collector currents of the NPN transistors 8 and 9 are I ₈ and I ₉ , respectively. Change the collector current of ΔI ₈ and Δ
As I ₉ , the output voltage V _{o at the} output terminal 51 is given by the following equation.

ΔI ₈ = nV _i / R ₆ ……………………………… (8) ΔI ₉ = (1-n) V _i / R ₆ ………………………… (9) Therefore, the output voltage V _{o at the} output terminal 51 is given by the following equation.

[0019] _{V o = V i R 15 /} R 6 -R 6 ΔI 9 = V i R 15 / R 6 - (1-n) V i R 15 / R 6 = nV i R 15 / R 6 ......... ………………………… (10) As is clear from the above equation, the input voltage V _i is V _i > V ₁
= R ₆ when it is in the region of (I ₁₄ -I _4), the voltage gain is NR15 / R6, and the input voltage V _i is 0 ≦ V _i of the foregoing
Compared with the case of being in the level range of <V ₁ , the voltage gain becomes n (n <1) times, and the voltage gain falls. That is, as seen in FIG. 2B, the output voltage V _o
Changes with n (R ₁₅ / R ₆ ) as a proportional constant. In the present invention, by changing the apparent voltage gain by feeding back a current of (1-n) times the inverted signal current to the output terminal side with the constant current value giving the knee point voltage as a boundary. The desired output signal waveform is obtained.

[0020]

As described above, according to the present invention, a shunt rectification circuit connected in series is provided in one amplification circuit of a differential amplifier, and the shunt rectification circuit is connected to the load resistance connected in series to the output side of the differential amplifier. Decreasing the apparent voltage gain by proportionally increasing the current through the shunt rectifier circuit in response to an input voltage exceeding the knee point voltage, and clearly setting the knee point in the output voltage. There is an effect that can be.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing operating characteristics in the present embodiment.

FIG. 3 is a circuit diagram showing a conventional example.

FIG. 4 is a diagram showing operating characteristics in a conventional example.

[Explanation of symbols]

 1, 16 Differential amplifier 2, 3, 8, 9, 17, 18 NPN transistor 4, 5, 14, 19, 20 Constant current source 6, 15, 21-23 Resistor 7 Shunt rectification circuit 10, 17, 18 PNP transistor 11, 12, 25, 26 Constant voltage source 13, 27 Input signal source 24 Diode

Claims (1)

[Claims] 1. A first and second emitter whose emitters are connected to each other by an emitter resistor corresponding to a predetermined input signal source.
Differential amplifier including the NPN transistor described above, the constant current source being inserted and connected between the high potential DC power supply and the collector of the first NPN transistor, and a differential amplifier formed using the collector of the second NPN transistor as an output terminal. A load resistor connected in series between the high potential DC power supply and the output terminal, a base commonly connected to the positive side of a predetermined constant voltage source, and an emitter both connected to the collector of the first NPN transistor. A third common connection and a collector individually connected to the high potential DC power supply and the output terminal, respectively.
And a fourth NPN transistor, and an PNP having an emitter connected to the collector of the first NPN transistor, a base connected to the bases of the third and fourth NPN transistors, and a collector connected to a ground potential. A nonlinear amplifier comprising: a transistor.