JPH05108549A - Access method for memory - Google Patents

Abstract

(57) [Summary] [Object] To provide a method of writing and reading a large amount of data to and from a memory at high speed in a memory access method of the cycle steal method. [Structure] In a memory access method of the cycle stealing method, in which data is written to a memory and data is read from the memory in alternate instruction cycles and direct memory access cycles, in a direct memory access cycle, a plurality of units from the memory Read the data for each minute,
The data is latched, and the latched data for each unit is read for each predetermined unit in the instruction cycle and the direct memory cycle.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to improvement of a memory access method of the cycle steal method.

[0002]

2. Description of the Related Art Under the control of a microcomputer (CPU: central processing unit), data stored in a data memory is written in a frame memory, the data stored in the frame memory is read out and transferred to a display. As a conventional example of a frame memory access method in the case of displaying as a display, there are a two division method and a cycle steal method. These conventional examples will be described with reference to the timing chart of FIG.

In the two-division method, data is written in a frame memory under the control of the microcomputer during the horizontal blanking period of the horizontal scanning period when the display is performed by the scanning method, and the frame memory is written during the horizontal drawing period. The data D0, D1, D2, ... Are read from the above, latched in the latch circuit by the latch clock signal of a predetermined frequency, read out, transferred to the display and displayed.

In the cycle stealing method, alternating instruction cycles (the period in which the CPU occupies the bus) and direct memory access cycles are provided within the horizontal scanning period when the display is performed by the scanning method. Write data to frame memory under control,
In the direct memory access cycle, data D0, D1, D2, ... are read from the frame memory and latched at a predetermined frequency (half the frequency of the latch clock signal in the case of the two division method). It is latched in a latch circuit by a clock signal, read out and transferred to a display for display.

[0005]

In the case of the two-division method, when the number of pixels displayed on the display is large, the amount of data to be written in the frame memory is large, so that the time required for writing is considerably long. Therefore, the display field frequency of the display is considerably lowered. Further, when a moving image is displayed on the display, the writing of data to the frame memory itself may be too late. Further, the read timing from the frame memory is adjusted to the scan timing of the display, but in that case, the occupied time of the direct memory access cycle becomes long, and therefore the instruction cycle becomes short and the microcomputer The processing capacity will decrease.

Further, in the case of the cycle steal method, there is a waste that the data read from the frame memory is not transferred to the display in the instruction cycle.

In view of the above point, the present invention writes data in the memory in alternate instruction cycles and direct memory access cycles,
In a memory access method of the cycle steal method in which data is read from the memory, a method capable of writing and reading a large amount of data to and from the memory at high speed is proposed.

[0008]

SUMMARY OF THE INVENTION The present invention relates to a cycle steal method memory access method for writing data to a memory and reading data from the memory in alternate instruction cycles and direct memory access cycles. In the direct memory access cycle, a plurality of units of data are read from the memory, latched respectively, and the latched data of a plurality of units are
In the instruction cycle and the direct memory cycle, a predetermined unit is read out.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The timing chart of FIG. 1 and FIG.
Embodiments of the present invention will be described in detail with reference to the circuit of FIG.
As shown in FIG. 1, alternate instruction cycles and direct memory access cycles are set in the horizontal scanning period of the display scanning of the display 3 of FIG.

The main control section 1 is composed of a microcomputer (CPU) 4 and a data memory 5,
Under the control of the microcomputer 4, the data read from the memory 5 is written in the frame memory 7 of the display control unit 2 in the instruction cycle.

A control signal from the microcomputer 4 is supplied to the display controller 6. Then, under the control of the display controller 6, an address signal is supplied to the frame 7 at high speed, and in the direct memory access cycle, for example, two units (three units or more) of data (data 1) can be supplied from the frame memory 7. ) D0:
D1, D2: D3, ... Are read and latched by the latch circuits 8 and 9, respectively. The display controller 6 controls the scanning period, the number of rows, etc. of the display 3.

The data D0: D1, D2: D3, which is latched by the latch circuits 8 and 9 for every two units, is ...
Is read by the latch clock signal signal of the same frequency as the cycle steal method in units of one unit (two units or more are possible) in each of the instruction cycle and the direct memory cycle, and is switched by the multiplexer 10 to output the data D0, D1, D2, D3, ‥‥‥
... is transferred to the display (CRT, LCD, plasma display, etc.) 3 and displayed.

According to such a memory access method, a large amount of data can be written in and read from the frame memory 7 at high speed. Large pixel display 3
In addition, the data can be supplied at high speed from the frame memory 7. Little decrease in processing speed of peripheral controller. The existing display controller can be used.

The present invention can be applied to other than the display memory.

[0015]

According to the present invention, in the memory access method of the cycle stealing method, the data is written to the memory and the data is read from the memory in the alternate instruction cycle and the direct memory access cycle. On the other hand, a large amount of data can be written and read at high speed. Moreover, it is not necessary to shorten the instruction cycle.

[Brief description of drawings]

FIG. 1 is a timing chart of a conventional example and an example of the present invention.

FIG. 2 is a block diagram showing an embodiment of the present invention.

[Explanation of symbols]

 1 Main Control Section 2 Display Control Section 3 Display 4 Microcomputer (CPU) 5 Memory 6 Display Control Section 7 Frame Memory 8 Latch Circuit 9 Latch Circuit 10 Multiplexer

Claims (1)

[Claims] 1. A memory access method of a cycle stealing method, wherein data is written to a memory and data is read from the memory in alternate instruction cycles and direct memory access cycles, and in the direct memory access cycle, A plurality of units of data are read out from the memory and latched respectively, and the latched plurality of units of data are read out every predetermined unit in the instruction cycle and the direct memory cycle. Memory access method.