JPH05108552A - Semiconductor integrated circuit device - Google Patents

Abstract

(57) [Summary] [Object] An object of the present invention is to reduce the parasitic capacitance of a bus and to speed up data transfer. [Structure] A semiconductor integrated circuit device is provided with a plurality of divided buses B0 to B3. Transfer gates T10, T20, T30, T12, T1 between buses
3, T23 selectively connect. Circuit blocks BL0 to BL3 are connected to the divided buses B0 to B3. When one circuit block is designated as a data transfer source and another one circuit block is designated as a data transfer destination, one transfer gate is turned on according to the designation, and the corresponding buses are connected to each other. Link. This selects only the buses involved in the data transfer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to improvement of a semiconductor integrated circuit device having a data transfer bus.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram showing a configuration around a data transfer bus in a conventional semiconductor integrated circuit device. In the figure, a plurality of circuit blocks BL0 to BL3 are connected to a data transfer bus (hereinafter, simply referred to as a bus) B. Each circuit block includes at least one logic circuit (eg, register). Circuit block BL
0 includes registers R00 to R0i. Circuit block B
L1 includes registers R10 to R1j. The circuit block BL2 includes registers R20 to R2k. The circuit block BL3 includes registers R30 to R3l. Each register is connected to the bus B, and data can be transferred between any registers.

Next, the operation of the conventional semiconductor integrated circuit device shown in FIG. 2 will be described. For example, circuit block B
When transferring data from the register R00 in L0 to the register R21 in the circuit block BL2, the register R00 is designated as the source of data transfer, and the register R2
1 is designated as the destination of the data transfer. At this time, the data held in the register R00 is sent to the bus B by the bus drive buffer in the register R00. When the potential of the bus B changes and its logic level is determined, the register R21 takes in the data of the bus B. When transferring data between other registers, the same operation as described above is performed.

[0004]

Since the conventional semiconductor integrated circuit device is configured as described above, if the degree of integration increases and the number of registers connected to the bus increases, the parasitic capacitance of the bus increases. To do. Therefore, from register to bus B
It takes a long time for the potential of the bus to reach a predetermined logic level when the data is sent to. Such a delay in the responsiveness of the bus potential may limit the speed performance of the entire semiconductor integrated circuit device, and there is a problem that the speedup of the semiconductor integrated circuit device is hindered.

Therefore, an object of the present invention is to provide a semiconductor integrated circuit device which can execute data transfer via a bus at high speed.

[0006]

A semiconductor integrated circuit device according to the present invention is divided into n (n is an integer of 2 or more) buses and is connected to each bus to transmit and / or receive transfer data. A plurality of circuit means for performing, and a bus connection control means for selectively connecting corresponding buses in response to designation of the circuit means for sending data and the circuit means for receiving data. Is equipped with.

[0007]

In the present invention, only buses involved in data transfer are selected and connected to each other, and data passes therethrough, so that the parasitic capacitance of the bus is reduced and high-speed data transfer becomes possible.

[0008]

1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, this semiconductor integrated circuit device includes a plurality of (four in the figure) divided buses B0 to B0.
It is equipped with B3. A circuit block is connected to each bus. The circuit block BL0 is connected to the bus B0, the circuit block BL1 is connected to the bus B1, the circuit block BL2 is connected to the bus B2, and the circuit block BL3 is connected to the bus B3. Each circuit block BL0-B
L3 includes a plurality of logic circuits (for example, registers) similarly to the circuit blocks shown in FIG. A transfer gate composed of, for example, a MOS transistor is interposed between the buses. A transfer gate T10 is inserted between the buses B0 and B1. Bus B
Transfer gate T20 is connected between 0 and bus B2.
Is inserted. A transfer gate T30 is inserted between the bus B0 and the bus B3. Bus B1 and Bus B2
A transfer gate T12 is inserted between the above and. A transfer gate T13 is inserted between the bus B1 and the bus B3. A transfer gate T23 is inserted between the bus B2 and the bus B3. Transfer gate T10, T20, T30, T12, T1
3, T23 are selection signals φ10, φ20, φ, respectively.
ON / OFF is controlled by 30, φ12, φ13, and φ23.

Next, the operation of the embodiment shown in FIG. 1 will be described. For example, the register R in the circuit block BL1
A case of transferring data from 10 to the register R31 in the circuit block BL3 will be described. In this case, the register R10 is designated as the data transfer source, and the register R31 is designated as the data transfer destination. Further, of the six selection signals, only the selection signal φ13 is activated. According to the transfer gate T13
Is turned on, and the buses B1 and B3 are connected via the transfer gate T13. Then, the bus drive buffer in the register R10 causes the data held in the register R10 to pass through the path of the bus B1 → the transfer gate T13 → the bus B3 and the circuit block BL.
3 is transmitted. At this time, buses B1 and B3 are charged / discharged by the bus drive buffer in register R10. When the logical levels of the buses B1 and B3 are determined after sending the data, the register R31 takes in the data of the bus B3.

When data is transferred between the other registers, the data is transferred in the same manner as described above.
That is, the transfer gates provided between the buses corresponding to the source register and the destination register are turned on to connect these buses.

When the register designated as the source and the register designated as the destination are connected to the same bus, for example, circuit block B is used.
When performing data transfer between the registers R20 and R21 in L2, it is not necessary to turn on any transfer gate.

Although the above embodiment includes four buses B0 to B3 as divided buses, the number of divided buses may be any number. Also, a plurality of circuit blocks may be connected to each of the divided buses.

Further, the transfer gate connecting the buses may be composed of one MOS transistor as in the above embodiment, or may be composed of a multidirectional transfer buffer circuit having a waveform shaping capability. ..

Further, each circuit block may be functionally separated, or the same functional unit may be divided.

Furthermore, the longest delay time can be reduced by making the parasitic capacitance values of the divided buses as uniform as possible.

[0016]

As described above, according to the present invention, only the buses involved in data transfer are selected and connected, so that the parasitic capacitance value of the bus charged and discharged in one data transfer can be reduced. As a result, the data transfer time is shortened and the power consumed for charging and discharging the parasitic capacitance of the bus is reduced. Further, since the charge / discharge current due to the parasitic capacitance of the bus at the time of data transfer is reduced, reliability problems such as electromigration can be avoided without increasing the bus wiring width. As a result, the parasitic capacitance of the bus wiring itself can be minimized, and high speed and high integration can be achieved at the same time.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration around a data transfer bus in a conventional semiconductor integrated circuit device.

[Explanation of symbols]

B0 to B3 ... Data transfer bus BL0 to BL3 ... Circuit block T10, T20, T30, T12, T13, T23 ... Transfer gate

Claims (1)

[Claims] 1. A divided n (n is an integer of 2 or more) data transfer bus, and a plurality of circuit means connected to each of the buses for sending and / or receiving transfer data, Bus connection control means for selectively connecting between corresponding buses in response to designation of the circuit means for sending data and the circuit means for receiving data.
Semiconductor integrated circuit device.