JPH05110618A - Digital line terminating equipment - Google Patents

Digital line terminating equipment

Info

Publication number
JPH05110618A
JPH05110618A JP3293568A JP29356891A JPH05110618A JP H05110618 A JPH05110618 A JP H05110618A JP 3293568 A JP3293568 A JP 3293568A JP 29356891 A JP29356891 A JP 29356891A JP H05110618 A JPH05110618 A JP H05110618A
Authority
JP
Japan
Prior art keywords
circuit
input power
reference clock
signal
processing circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3293568A
Other languages
Japanese (ja)
Other versions
JP2731646B2 (en
Inventor
Makoto Kadowaki
眞 門脇
Yasuo Miyajima
靖夫 宮島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Platforms Ltd
NEC Corp
Original Assignee
NEC Corp
NEC AccessTechnica Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, NEC AccessTechnica Ltd filed Critical NEC Corp
Priority to JP3293568A priority Critical patent/JP2731646B2/en
Publication of JPH05110618A publication Critical patent/JPH05110618A/en
Application granted granted Critical
Publication of JP2731646B2 publication Critical patent/JP2731646B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Communication Control (AREA)
  • Maintenance And Management Of Digital Transmission (AREA)

Abstract

PURPOSE:To miniaturize a function block for holding an output voltage just after input power interruption and to increase profitability. CONSTITUTION:This equipment is provided with a clock generating circuit 5 frequency-dividing the output signal of a VCXO 4 and generating a reference clock, a frame transmission section 3 operated by receiving the reference clock and generating and sending a frame to inform an input power supply interruption signal outputted to an opposite device, and other signal processing circuit 6 operated through the reception of the reference clock. Then an inhibiting circuit 1 for blocking the input of the reference clock to the other processing circuit 6 by the entry of the input power supply interruption signal is interposed between the clock generating circuit 5 and the other processing circuit 6.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、ディジタル回線終端装
置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital line terminal device.

【0002】[0002]

【従来の技術】図2に、従来のディジタル回線終端装置
の構成が示されている。この図2において、電圧制御水
晶発振器(以下、「VCXO」という。)4の出力はク
ロック発生回路5で分周され、基準クロックとなって、
電源部2から入力電源断状態になった場合に出力される
入力電源断信号を図示しない対向装置へ通知するためフ
レーム組立を行うフレーム送信部3と、他の信号処理回
路6(これは、ここでは一つしか図示していないが、実
際には複数ある場合が多い。)との両方のブロックへ常
時供給されるようになっていた。
2. Description of the Related Art FIG. 2 shows the configuration of a conventional digital line terminating device. In FIG. 2, the output of a voltage controlled crystal oscillator (hereinafter referred to as “VCXO”) 4 is divided by a clock generation circuit 5 to become a reference clock,
A frame transmission unit 3 that performs frame assembly to notify an opposite device (not shown) of an input power cutoff signal output when the power supply unit 2 is in an input power cutoff state, and another signal processing circuit 6 (this is here. , Only one is shown in the figure, but there are many cases in practice.)

【0003】[0003]

【発明が解決しようとする課題】上述した従来のディジ
タル回線終端装置では、入力電源断信号を図示しない対
向装置へ通知するためフレーム組立を行うフレーム送信
部3と他の信号処理回路6との両者へ常時作動のための
基準クロックが供給されていることから、入力電源断状
態になった後、対向装置へ入力電源断情報を通知するフ
レーム送信部3の動作中の一定時間は、図中符号7で示
す装置内の他のすべての信号処理回路が動作するように
なっている。このため、入力電源断直後に消費される電
力が大きくなり、当該入力電源断直後の出力電圧のため
の機能ブロック,即ち電源部2を構成する出力電圧保持
回路等の小型化が困難であるという不都合があった。
In the above-mentioned conventional digital line terminating device, both the frame transmitting section 3 for assembling the frame and the other signal processing circuit 6 for assembling the input power-off signal to the opposite device (not shown). Since the reference clock for constant operation is supplied to the device, the fixed time during the operation of the frame transmission unit 3 that notifies the other device of the input power cutoff information after the input power cutoff state is represented by the symbol in the figure. All other signal processing circuits within the device shown at 7 are operative. For this reason, the power consumed immediately after the input power is cut off is large, and it is difficult to downsize the functional block for the output voltage immediately after the input power cut off, that is, the output voltage holding circuit or the like that constitutes the power supply unit 2. There was an inconvenience.

【0004】[0004]

【発明の目的】本発明の目的は、かかる従来技術の有す
る不都合を改善し、入力電源断直後の出力電圧保持のた
めの機能ブロックの小型化及び経済化を図ることができ
るディジタル回線終端装置を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a digital line terminating device capable of improving the disadvantages of the prior art and reducing the size and cost of the function block for holding the output voltage immediately after the input power is cut off. To provide.

【0005】[0005]

【課題を解決するための手段】本発明のディジタル回線
終端装置は、発振器の出力信号を分周して基準クロック
を生成するクロック発生回路と、基準クロックを受けて
動作し電源部から入力電源断状態になった場合に出力さ
れる入力電源断信号を対向装置へ通知するためフレーム
を生成し送信するフレーム送信部と、基準クロックを受
けて動作する他の信号処理回路とを備えている。そし
て、クロック発生回路と他の信号処理回路との間には、
入力電源断信号の入力により基準クロックがフレーム送
信部以外の他の信号処理回路へ入力されるのを阻止する
禁止回路が介装されている。このような構成によって、
前述した目的を達成しようとするものである。
SUMMARY OF THE INVENTION A digital line terminating device of the present invention comprises a clock generating circuit for dividing an output signal of an oscillator to generate a reference clock, and an operation for receiving the reference clock to cut off input power from a power supply section. A frame transmission unit that generates and transmits a frame for notifying the opposite device of the input power-off signal that is output when the status becomes a state, and another signal processing circuit that operates by receiving the reference clock. And, between the clock generation circuit and the other signal processing circuit,
A prohibiting circuit is interposed to prevent the reference clock from being input to other signal processing circuits other than the frame transmitting unit by the input of the input power-off signal. With this configuration,
It is intended to achieve the above-mentioned purpose.

【0006】[0006]

【実施例】以下、本発明の一実施例を図1に基づいて説
明する。ここで、前述した従来例と同一の構成部分につ
いては、同一の符号を付すものとする。
DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. Here, the same components as those in the conventional example described above are denoted by the same reference numerals.

【0007】この図1に示す実施例は、発振器としての
VCXO4の出力信号を分周して基準クロックを生成す
るクロック発生回路5と、基準クロックを受けて動作し
電源部1から入力電源断状態になった場合に出力される
入力電源断信号を図示しない対向装置へ通知するためフ
レームを生成し送信するフレーム送信部3と、基準クロ
ックを受けて動作する他の信号処理回路6とを備えてい
る。そして、クロック発生回路5と他の信号処理回路6
との間には、入力電源断信号の入力により基準クロック
がフレーム送信部3以外の他の信号処理回路6へ入力さ
れるのを阻止する禁止回路1が介装されている。
In the embodiment shown in FIG. 1, a clock generation circuit 5 which divides an output signal of a VCXO 4 as an oscillator to generate a reference clock, and a state in which an input power is cut off from a power supply section 1 by receiving the reference clock and operating. And a signal processing circuit 6 for receiving a reference clock and operating to generate a frame for notifying an opposite device of an input power-off signal output when There is. Then, the clock generation circuit 5 and the other signal processing circuit 6
A prohibiting circuit 1 for preventing the reference clock from being input to a signal processing circuit 6 other than the frame transmitting section 3 by the input of the input power-off signal is interposed between the and.

【0008】次に、動作を説明すると、入力電源投入状
態から入力電源断状態へと切り替わると、電源部2では
これを検出して入力電源断信号をフレーム送信部3へ出
力する。この時、クロック発生回路5から出力される基
準クロックがフレーム送信部3へ供給されているので、
フレーム送信部3が作動し、入力電源断信号を通知する
ためのフレームが生成,送信される。これにより、入力
電源断信号が図示しない対向装置(局側)へ通知され
る。電源部2からは、入力電源断信号が禁止回路1にも
送出されているので、禁止回路1では、入力電源断信号
の入力により他の信号処理回路6への基準クロックの入
力を阻止する。このため、フレーム送信部3以外の他の
信号処理回路6へは基準クロックが入力されず、他の信
号処理回路6は動作を停止する。
Next, the operation will be described. When the input power is switched from the input power-on state to the input power-off state, the power supply unit 2 detects this and outputs the input power-off signal to the frame transmission unit 3. At this time, since the reference clock output from the clock generation circuit 5 is supplied to the frame transmission unit 3,
The frame transmitter 3 operates to generate and transmit a frame for notifying the input power-off signal. As a result, the input power-off signal is notified to the opposite device (station side) not shown. Since the input power-off signal is also sent from the power supply unit 2 to the prohibition circuit 1, the prohibition circuit 1 blocks the reference clock from being input to the other signal processing circuits 6 by the input of the input power-off signal. Therefore, the reference clock is not input to the signal processing circuits 6 other than the frame transmitting unit 3, and the other signal processing circuits 6 stop operating.

【0009】以上説明したように本実施例によると、入
力電源断直後には、フレーム送信部3以外の他の信号処
理回路6が動作を停止するので、入力電源断直後に消費
される電力が低くなり、電源部2での出力電圧保持のた
めの機能ブロック(電源部2を構成する出力電圧保持回
路等)の小型化・経済化が可能となる。
As described above, according to this embodiment, since the signal processing circuits 6 other than the frame transmission unit 3 stop operating immediately after the input power is cut off, the power consumed immediately after the input power supply is cut off. As a result, the function block for holding the output voltage in the power supply unit 2 (such as the output voltage holding circuit forming the power supply unit 2) can be downsized and made economical.

【0010】ここで、装置を構成する回路、特に他の信
号処理回路6がMOSゲート論理回路であれば、入力電
源断直後の消費電力をより一層低減させることができ
る。
Here, if the circuit forming the device, especially the other signal processing circuit 6 is a MOS gate logic circuit, the power consumption immediately after the input power is cut off can be further reduced.

【0011】[0011]

【発明の効果】以上説明したように、本発明によれば、
入力電源断直後には、禁止回路の機能によりフレーム送
信部以外の他の信号処理回路への動作のための基準クロ
ックの入力を阻止することができ、これにより当該他の
信号処理回路の動作を停止せしめることができることか
ら電源入力断直後に消費される電力の低減を図ることが
でき、電源部での出力電圧保持のための機能ブロックの
小型化・経済化が可能となり、ひいては装置全体の小型
・経済化をも図ることができるという従来にない優れた
ディジタル回線終端装置を提供することができる。
As described above, according to the present invention,
Immediately after the input power is turned off, the input of the reference clock for the operation to the signal processing circuits other than the frame transmission unit can be blocked by the function of the prohibition circuit, and thus the operation of the other signal processing circuits can be prevented. Since it can be stopped, it is possible to reduce the power consumed immediately after the power input is cut off, and it is possible to make the functional block for maintaining the output voltage in the power supply unit smaller and more economical, which in turn reduces the overall size of the device. -It is possible to provide an excellent digital line terminal device that has not been available in the past and that can be made economical.

【0012】特に、請求項2記載の発明にあっては、入
力電源断直後の消費電力をより一層低減させることがで
きるという効果がある。
In particular, the invention according to claim 2 has an effect that the power consumption immediately after the input power is cut off can be further reduced.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例の構成を示すブロック図であ
る。
FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

【図2】従来例の構成を示すブロック図である。FIG. 2 is a block diagram showing a configuration of a conventional example.

【符号の説明】[Explanation of symbols]

1 禁止回路 2 電源部 3 フレーム送信部 4 発振器としてのVCXO 5 クロック発生回路 6 他の信号処理回路 1 inhibit circuit 2 power supply section 3 frame transmission section 4 VCXO as oscillator 5 clock generation circuit 6 other signal processing circuit

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 発振器の出力信号を分周して基準クロッ
クを生成するクロック発生回路と、前記基準クロックを
受けて動作し電源部から入力電源断状態になった場合に
出力される入力電源断信号を対向装置へ通知するためフ
レームを生成し送信するフレーム送信部と、前記基準ク
ロックを受けて動作する他の信号処理回路とを備えたデ
ィジタル回線終端装置において、前記クロック発生回路
と他の信号処理回路との間に、前記入力電源断信号の入
力により前記基準クロックが前記他の信号処理回路へ入
力されるのを阻止する禁止回路を介装したことを特徴と
するディジタル回線終端装置。
1. A clock generation circuit that divides an output signal of an oscillator to generate a reference clock, and an input power cutoff that is operated when receiving the reference clock and output from a power supply unit in an input power cutoff state. In a digital line terminating device comprising a frame transmitting unit for generating and transmitting a frame for notifying a signal to a counter device, and another signal processing circuit which operates by receiving the reference clock, the clock generating circuit and other signals A digital line terminating device, wherein a prohibiting circuit for preventing the reference clock from being input to the other signal processing circuit by the input of the input power-off signal is interposed between the processing circuit and the processing circuit.
【請求項2】 前記他の信号処理回路が、MOSゲート
論理回路により構成されていることを特徴とした請求項
1記載のディジタル回線終端装置。
2. The digital line terminating device according to claim 1, wherein the other signal processing circuit comprises a MOS gate logic circuit.
JP3293568A 1991-10-14 1991-10-14 Digital line termination equipment Expired - Lifetime JP2731646B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3293568A JP2731646B2 (en) 1991-10-14 1991-10-14 Digital line termination equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3293568A JP2731646B2 (en) 1991-10-14 1991-10-14 Digital line termination equipment

Publications (2)

Publication Number Publication Date
JPH05110618A true JPH05110618A (en) 1993-04-30
JP2731646B2 JP2731646B2 (en) 1998-03-25

Family

ID=17796430

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3293568A Expired - Lifetime JP2731646B2 (en) 1991-10-14 1991-10-14 Digital line termination equipment

Country Status (1)

Country Link
JP (1) JP2731646B2 (en)

Also Published As

Publication number Publication date
JP2731646B2 (en) 1998-03-25

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Effective date: 19971202