JPH05114853A - Low noise output drive circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide an output drive circuit with low noise. [Structure] A source potential supply circuit having a means for dropping the voltage and a means for eliminating the voltage drop by shorting both ends thereof is provided on the power supply side of a drive circuit of a normal CMOS inverter configuration, and the voltage drop is initially provided. Control it to have it and then to make it 0. According to this configuration, since the drive circuit initially includes the voltage drop, it does not completely swing to the power supply potential, and then the voltage drop becomes 0 and reaches the power supply potential. This method suppresses excessive transient current when the output changes and eliminates overshoot and undershoot. [Effect] As described above, the transient current is reduced and the noise is reduced. Further, since the output level is in two stages, there is also an effect of reducing power consumption due to charge / discharge of the capacitive load.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to noise reduction of an output drive circuit in a semiconductor integrated circuit.

[0002]

2. Description of the Related Art A complementary output drive circuit using a conventional insulated gate field effect transistor (hereinafter abbreviated as MOSFET) connects a source electrode of a P-type MOSFET to a positive power supply terminal + VDD as shown in FIG. The source electrode of the N-type MOSFET is connected to the negative power supply terminal -VSS, and the drain electrodes and the gate electrodes of the P-type and N-type MOSFETs are connected to each other.

[0003]

In the above-mentioned conventional circuit, the output potential swings from + VDD to -VSS to the full power supply as shown in FIG. 4, and transiently exceeds the power supply potential to cause overshoot. Since undershoot is caused, there is a problem that the driving capability is increased and the noise due to the transient current when the output potential changes becomes excessive and adversely affects other circuits.

Therefore, the present invention solves such a problem, and an object of the present invention is to provide an output drive circuit in which noise is less generated due to a transient current when the output potential changes.

[0005]

The low noise drive circuit of the present invention is a) a semiconductor integrated circuit using an insulated gate field effect transistor, and b) a P-type MOSFET and an N-type MO.
A drive circuit including an SFET; c) a positive source potential supply circuit for controlling the source potential of a P-type MOSFET in the drive circuit; and d) an N-type MOSFE in the drive circuit.
A negative source potential supply circuit for controlling the source potential of T;
e) a delay circuit, f) input terminals are connected to respective input signal terminals of the drive circuit and the delay circuit, and output signal terminals of the delay circuit are the positive source potential supply circuit and the negative source potential supply circuit. Are connected to respective control signal terminals of.

[0006]

According to the above configuration of the present invention, the output potential of the drive circuit does not swing to the full power supply potential in the first stage of switching, and reaches the power supply potential in the next stage. It is possible to suppress an excessive transient current at the time of changing, and there is no overshoot or undershoot, and an output drive circuit with less noise is generated.

[0007]

1 is a circuit diagram showing a first embodiment of the present invention. In FIG. 1, the circuit surrounded by a broken line 10 is a drive circuit, the circuit surrounded by a broken line 11 is a positive source potential supply circuit, the circuit surrounded by a broken line 12 is a negative source potential supply circuit, and a broken line 13 The circuit surrounded by is the delay circuit. In the drive circuit 10, the P-type MOSFET 16 and N
The gate electrodes of the type MOSFET 19 are connected to each other and to the input terminal 14. The drain electrodes are also connected to each other and to the output terminal 15.
The positive source potential supply circuit 11 is composed of P-type MOSFETs 17 and 18. P-type MOSFETs 17 and 18
Of the P-type MOSFET 16 in the drive circuit 10 are connected to the positive power supply electrode + VDD and their drain electrodes are connected to each other.
Connected to the source electrode of. Also P-type MOSFET
The gate electrode of 17 is connected to the drain electrode, and the threshold voltage VTP is applied between the source electrode and the drain electrode.
Is configured to generate. P-type MOSFET 18
Serves as a switch which is turned on (ON) and turned off (OFF) depending on whether the signal of the gate electrode is low potential or high potential. The negative source potential supply circuit 12 is an N-type MOSFET 2
It consists of 0 and 21. The source electrodes of the N-type MOSFETs 20 and 21 are both negative power supply electrodes -V.
N-type MOSFET in the drive circuit 10 connected to SS and each drain electrode connected to each other
It is connected to 19 source electrodes. Also N-type MOSF
The gate electrode of ET20 is connected to the drain electrode, and is configured to generate a threshold voltage VTN between the source electrode and the drain electrode. N-type MOSFE
T21 serves as a switch that is turned on and off depending on whether the signal of the gate electrode is high potential or low potential. Delay circuit 1
3 is composed of inverter circuits 22 and 23. The signal at the input terminal 14 is connected to the input signal terminal of the inverter circuit 22, the output signal terminal of the inverter circuit 22 is the output signal terminal of the inverter circuit 23, and the P-type MOSFET is the output signal terminal.
18 and the gate electrodes of the N-type MOSFET 21.

Now, when a low potential signal is input to the input terminal 14, the N-type MOSFET 19 is immediately turned off and the P-type MOSFET is turned on.
T16 turns on immediately. However, at this time, P-type MOSFE
Since T18 is off due to the delay circuit 13, current is supplied to the output terminal 15 through the P-type MOSFETs 17 and 16, and the output terminal 15 is caused by the difference VTP between the source and drain of the P-type MOSFET 17. The potential level of the voltage rises only to (VDD-VTP). After that, when the gate electrode of the P-type MOSFET 18 becomes low potential through the delay circuit 13, the P-type MOSFET 18 is turned on and the potential level of the output terminal 15 reaches VDD. The above waveform is the waveform at the time of rising in FIG.

When a high-potential signal is input to the input terminal 14, the P-type MOSFET 16 immediately turns off and the N-type MOSFE is turned on.
T19 turns on immediately. However, at this time, N-type MOSF
Since the ET 21 is off due to the delay circuit 13, the output terminal 15 is supplied with current through the N-type MOSFETs 20 and 19, and the source / source of the M-type MOSFET 20.
Due to the potential difference VTN between the drains, the potential level of the output terminal 15 drops only to VTN. After that, the N-type MOSFET 21 in which the gate electrode of the N-type MOSFET 21 has a high potential is turned on through the delay circuit 13, and the potential level of the output terminal 15 reaches 0 potential. The above waveform is depicted in the waveform at the time of the fall in FIG.

As described above, in the case of rising, first (VDD-V
After the output potential rises to TP), it reaches VDD after a short time, and in the case of a fall, the output potential first drops to VTN and then reaches 0 potential after a while. Therefore, it can be seen that the transient current is suppressed to a low level when the output potential changes, and the output drive circuit has low noise without overshoot or undershoot.

The power consumption due to charging / discharging when a capacitive load is applied to the output terminal will be described below.
If the frequency of the output signal is f, the power supply voltage is VDD, and the electrostatic capacity of the load is CL, the charging / discharging is repeated directly between the power supply voltages VDD as in the conventional circuit as shown in FIG.
O becomes PO = f · CL · VDD ² (101). On the other hand, at the time of rising as in the circuit of FIG. 1 which is the first embodiment of the present invention, first, the output terminal is (VDD-VTP).
For the sake of simplicity, VTH = VTP = V for the following reason.
If TN, the power consumption is f · CL · (VDD-VTH) ^{2 in} the first stage and f · CL · VTH ^{2 in} the second stage, so the total power consumption PN is PN = f · CL · (VDD- VTH) ² + f · CL · VTH ² (102). Therefore, the difference ΔP between the power consumption P0 of the conventional method and the current consumption PN of the method of the present invention is expressed by equations (101) and (1).
From the equation 02), ΔP = P0−PN = f · CL · 2 (VDD−VTH) VTH (103). Normally VDD> VTH and VTH> 0, so ΔP
> 0, that is, P0> PN (104). Therefore, it can be seen from the equation (104) that the circuit system of the present invention has lower power consumption for charging and discharging the capacitive load than the conventional circuit system.

Although the embodiment of the present invention has been described with reference to the circuit of FIG. 1, the present invention is not limited to the circuit of FIG. For example, since the inverter circuits 22 and 23 function as delay elements, they may be simple resistors, and any number of inverter circuits can be used if they are even numbers.

The driving ability of the P-type MOSFETs 16, 17, 18 and the N-type MOSFETs 19, 20, 21 and the delay time of the delay circuit 13 are determined by the driving ability, the slew rate and the allowable noise limit of the low noise output driving circuit of the present invention. The optimum value will be adjusted accordingly. Moreover, in FIG.
The voltage drop corresponding to the threshold voltage of
The FETs 17 and 20 having the structure may be serially connected in two stages to cause a double threshold voltage drop. It may also have other means for causing a voltage drop.

[0014]

As described above, according to the present invention, when the output potential is switched, the operation is first performed so that the power supply voltage is not completely swung, and then the output potential reaches the power supply potential. As a result, the transient current can be suppressed to a low level, and neither overshoot nor undershoot will occur. Therefore, there is an effect of providing an output drive circuit having high drive capability and low noise.

Further, since the load is charged / discharged in two output levels, there is an effect of reducing charge / discharge power.

Since the power consumption is reduced, heat generation can be suppressed,
In addition, it is possible to prevent changes in electrical characteristics and improve quality assurance.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is an output waveform diagram showing the operation of the circuit of FIG.

FIG. 3 is a circuit diagram of a conventional output drive circuit.

FIG. 4 is an output waveform diagram showing the operation of the circuit of FIG.

[Explanation of symbols]

 10 ... Drive circuit 11 ... Positive source potential supply circuit 12 ... Negative source potential supply circuit 13 ... Delay circuit 14 ... Input terminal 15 ... Output terminal 16, 17, 18 ... P-type MOSFETs 19, 20, 21 ... N-type MOSFETs

Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H03K 19/003 Z 8941-5J

Claims (1)

[Claims] 1. A semiconductor integrated circuit using an insulated gate field effect transistor (hereinafter abbreviated as MOSFET), b) a drive circuit including a P-type MOSFET and an N-type MOSFET, and c) one of the drive circuits. A positive source potential supply circuit for controlling the source potential of the P-type MOSFET, d) a negative source potential supply circuit for controlling the source potential of the N-type MOSFET in the drive circuit, and e) a delay circuit, and f) an input. The terminals are connected to the respective input signal terminals of the drive circuit and the delay circuit, and the output signal terminals of the delay circuit are connected to the respective control signal terminals of the positive source potential supply circuit and the negative source potential supply circuit. A low noise output drive circuit characterized in that