JPH0512011A - Pipeline circuit - Google Patents

Abstract

(57) [Summary] [Purpose] Flexible data processing is possible by arbitrarily changing the relationship between the data input order and the data output order and the relationship between the total number of data inputs and the total number of data outputs. [Structure] A memory bank 11 has three banks a, b and c for inputting / outputting data, and each bank a, b, c
The output end of is connected to the circuit blocks 12, 13, 14 and
The output terminals of the circuit blocks 12 and 13 are banks a, b, and
connected to c. The memory bank 11 is configured to be accessible from the circuit blocks 12, 13 and 14, and each circuit block stores the processing result in a predetermined bank in the memory bank 11. Further, the pointer indicating which bank is stored is transferred to the next stage, and the circuit block which receives the pointer of the bank processes the data in the bank indicated by the pointer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pipeline circuit used in various high speed digital processing circuits as one means for increasing the data processing speed.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram showing a configuration of a conventional pipeline circuit. In FIG. 2, the circuit block 1
Is connected to the register 2, the circuit block 1 performs the first stage processing, and the register 2 temporarily stores only one data output from the circuit block 1. The circuit block 3 connected to the register 2 is connected to the register 4, the circuit block 3 performs the second stage processing, and the register 4 temporarily stores only one data output from the circuit block 3. The circuit block 5 connected to the register 4 is the third
Perform the processing of the first stage.

The operation of the above configuration will be described below. First, in the circuit block 1, time-series data D1 of cycle T
When ~ D30 is input, each data is processed by the circuit block 1 and the time series data A (D1) to A (D30) of the cycle T is input.
Is output. This time series data A (D1) to A (D3
Each data of 0) is held in the register 2 for the time T, so that the time series data A (D
1) to A (D30) are delayed from the time series data D1 to D30 by the time T and output. Then, the time-series data A (D1) to
When A (D30) is input, each data is processed in the circuit block 3 and time series data B (D1) to B (D
30) is output. This time series data B (D1) to B
Each data of (D30) is held in the register 4 for the time T, so that the time series data B (D1) to B (D30) from the register 4 are time series data A (D1) to A.
Each is output after a delay of time T from (D30). Further, when the time series data B (D1) to B (D30) of the cycle T is input to the subsequent circuit block 5, each data is processed by the circuit block 5 and the time series data C (D1) to the cycle T. C (D30) is output.

Here, first, the time series data A (D1) processed by the circuit block 1 is held in the register 2, the circuit block 1 starts processing the next time series data D2, and the register 2 Time series data A in the circuit block 3
(D1) is output, and the circuit block 3 outputs the time series data A
Start processing (D1). And at a certain time,
If the circuit block 1 processes the data D4,
This means that the circuit block 3 at the subsequent stage is processing the data A (D3) and the circuit block 5 at the subsequent stage is processing the data B (D2).

Therefore, each circuit block 1, 3 and 5 is processing each data at the same time, and the data processing speed is improved by parallelizing such data processing.

[0006]

However, in the above conventional configuration, the total number of input time-series data and the total number of time-series data output as a result of data processing must be equal, and the time-series data There was a problem that the processing order had to be the same as the input order, and there was no flexibility in data processing.

The present invention is to solve the above-mentioned conventional problems, and to perform flexible data processing by arbitrarily changing the relationship between the data input order and the data output order and the relationship between the total data input and the total data output. It is an object of the present invention to provide a pipeline circuit capable of performing the above.

[0008]

In order to solve the above problems, a pipeline circuit according to the present invention is a pipeline circuit for sequentially performing data processing by a plurality of circuit blocks forming a pipeline. A data storage means is provided which is connected to each block and inputs and outputs data.

[0009]

With the above structure, since the data storage means for inputting and outputting the data is respectively connected to the plurality of circuit blocks, the data stored in the data storage means can be read and processed in any order. Is possible,
Further, since the data storage means is used for data transmission / reception between the stages of each circuit block forming the pipeline and the processing result of each circuit block is stored in the temporary data storage means, the processed data is increased or decreased with respect to the input data. But no problem.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a pipeline circuit according to an embodiment of the present invention. In FIG. 1, a memory bank 11 as a data storage means such as a memory and a register file has three banks a, b and c for inputting / outputting data, and the output terminals of the respective banks a, b and c are It is connected to the circuit blocks 12, 13 and 14, and the output ends of the circuit blocks 12 and 13 are banks a, b and c, respectively.
It is connected to the. The memory bank 11 is configured to be accessible from each processing stage of the pipeline, that is, the circuit blocks 12, 13, and 14, and the circuit blocks 12, 13 store the processing result in a predetermined bank in the memory bank 11. The circuit block 12 is connected to the circuit block 13 in the subsequent stage and the circuit block 14 in the subsequent stage, transfers the pointer indicating which bank is stored to the next stage, and the circuit block receiving the pointer of the bank is This is a configuration for processing the data in the bank indicated by the pointer.

The operation of the above arrangement will be described below. First, among the time series data D1 to D30, the memory bank 11 has time series data D1 to D10 in bank a, time series data D11 to D20 in bank b, and time series data D21 to D30 in bank c.
Is entered. When all the data is stored in the bank a, the circuit block 12 starts processing the data in the bank a and stores the processing result in the bank a. At the end of the processing, the circuit block 12 is stored in the circuit block 13 as a memory bank.
The pointer indicating the bank a of 11 is transferred. Circuit block
13 determines from this pointer that the data to be processed is stored in bank a. Then, the circuit block 13 starts the processing on the data in the bank a and stores the processing result in the bank a. Circuit block at the end of processing
13 transfers the pointer indicating the bank a of the memory bank 11 to the circuit block 14. The circuit block 14 determines from this pointer that the data to be processed is stored in the bank a. Then, the circuit block 14 starts the processing on the data in the bank a and outputs the processing result.

At a certain time, the circuit block 14
If the data is in the bank a, the circuit block 13 is processing the data in the bank b, and the circuit block 12 is processing the data in the bank c at the same time.

Therefore, each circuit block 12, 13, 14 is processing each data at the same time, and the processing speed can be improved by parallelizing such processing.
Further, since the input data is stored once in the data bank 11, the data can be read out from the data bank 11 in a required order and sequentially processed by the respective circuit blocks 12, 13, 14. That is, the data stored in the memory bank 11 can be read and processed in any order. Further, since the memory bank 11 is used for transmitting and receiving data between the stages of the pipeline, it is possible to generate as much data as the memory capacity of the data bank 11 allows. That is, since the processing result is stored in the temporary memory bank 11,
There is no problem even if the processed data increases or decreases with respect to the input data.

[0014]

As described above, according to the present invention, by providing the data storage means which is connected to each of a plurality of circuit blocks to input / output data, the input data is stored once in the data storage means. However, data can be read out from the data storage means in the required order and data processing can be performed in each circuit block, and the processing result of each circuit block can be stored in the data storage means as long as the memory capacity of the data storage means permits. It is possible to perform flexible data processing, such as generation of data.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a pipeline circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a conventional pipeline circuit.

[Explanation of symbols]

 11 memory banks 12, 13, 14 circuit blocks

Claims (1)

Claim: What is claimed is: 1. A pipeline circuit for sequentially performing data processing by a plurality of circuit blocks forming a pipeline, the data being connected to each of the plurality of circuit blocks to input and output data. A pipeline circuit provided with storage means.