JPH05120217A - Data communication device - Google Patents

Abstract

PURPOSE:To improve the operation efficiency of a transmission-side host processor. CONSTITUTION:In FIFO, this data communication device is equipped with plural memory cells 5-1-5-n corresponding to plural stages of buffers, a write counter 4 which generates and outputs a signal specifying a memory cell to be written among the memory cells 5-1-5-n and a write signal for the specified memory cell, a flip-flop 6 which holds information showing that transfer data are written in the memory cells 5-1-5-n in order until the transfer data are written in the final memory cell. A readout counter 7 which generates and outputs a signal specifying a memory cell to be read among the memory cells 5-1-5-n and a readout signal for the specified memory cell, and a flip-flop 8 which holds information showing that the all memory cells 5-1-5-n can be read.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data communication device,
In particular, it relates to a data communication device between host processors performed via a FIFO.

[0002]

2. Description of the Related Art In a conventional data communication apparatus of this type, as shown in FIG. 3, an F-channel is provided between a host processor A9 on the transmitting side and a host processor B11 on the receiving side.
An IFO 10 is provided, and data is exchanged via the internal bus A204 and the internal bus B205. In FIG. 3, when data is transferred from the host processor A9 on the transmission side to the host processor B11 on the reception side, the transmission data 113 is transmitted via the internal bus A204 and the write address pointer / reset signal 115 is transmitted. , And FIFO1 via write signal 116
0, and the received data 114 is read address pointer reset signal 117 and read signal 11
8 via the internal bus 205, and is received by the host processor B11. The host processor B11 detects the presence or absence of an error in the received data, and sends the error detection signal 119 to the host processor A9 on the transmitting side.

[0003]

In the conventional data communication apparatus described above, the FIFO 10 is supported in the steady state in which the data is transferred from the host processor A9 on the transmitting side to the host processor B11 on the receiving side. The operations on the write side and the read side are performed asynchronously, and are synchronized by adding information that is set at the time of writing and reset at the time of reading to the data. Therefore, in general, the read operation is also completed immediately after all the writing is completed. So, even if you have a hardware problem,
When erroneous data is written in the FIFO 10 and transmitted to the receiving side, the receiving side is forced to send an error detection signal to the transmitting side, and the host processor A9 on the transmitting side receives In this situation, there is no way to receive this error detection signal, sample the error detection signal one by one, and retransmit the signal.

To this end, the host processor A on the transmitting side
Not only is the data transfer program in No. 9 complicated, but the overhead time increases with the increase in data transfer and retransfer, and the original processing capacity is significantly reduced.

[0005]

A data communication apparatus according to the present invention is a data communication apparatus for transferring data via a FIFO, wherein a plurality of memory cells corresponding to a plurality of stages of buffers are provided inside the FIFO, and a transmission side. A write counter that generates and outputs a signal designating a memory cell to be programmed among the plurality of memory cells and a write signal to the designated memory cell in response to a data write signal output from the memory cell. , The transfer data is sequentially written into the plurality of memory cells, and first information holding means for holding information indicating that the transfer data has been written into the final memory cell, and output from the receiving side. A signal for designating a memory cell to be read out of the plurality of memory cells and a read signal for the designated memory cell. Configured to include a read counter for generating and outputting the door, and a second information holding means for said plurality of memory cell holds information indicating whether all is readable, the.

The first and second information holding means may be formed by flip-flops.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. As shown in FIG. 1, in this embodiment, an internal bus A201 involved in data exchange on the transmission side and an internal bus B202 involved in data exchange on the reception side.
Corresponding to, the host processor A1 on the transmission side and the FIF
It comprises O2 and a host processor B3 on the receiving side. 2 is a block diagram showing the internal configuration of the FIFO 2 shown in FIG. 1. As shown in FIG.
The FIFO 2 corresponds to the internal bus A201, and a write counter 4 for generating a signal designating a memory cell to be written and a write pulse, and n memory cells 5-1 corresponding to a buffer of n (positive integer) stages. ~ 5-n and the flip-flop 6 which holds the information written in the final memory
A read counter 7 for generating a signal for designating a memory cell to be read and a read pulse; and a flip-flop 8 for holding information indicating whether or not all memory cells can be read. .

A processing procedure for writing data in the FIFO2 from the host processor A1 on the transmitting side will be described below with reference to FIGS. 1 and 2.

First, on the transmitting side, the internal bus A20 is used.
It is confirmed whether the memory full signal 108 input via 1 is in the reset state, that is, whether all the memory cells are in the unreadable state. After that, the write address pointer
The reset signal 103 is output. In the FIFO 2, the write counter 4 is cleared in response to the write address pointer / reset signal 103. Then, the write signal 104 is input to the write counter 4 via the internal bus A201, and the transfer data is sequentially written to the n memory cells 5-1 to 5-n. For each of these memory cells, the write counter 4 is incremented (+1) every time the write signal 104 is input, and the memory cells 5-1 to 5-n are sequentially designated. Finally,
When the data is written in the last memory cell, the status bit in the flip-flop 6 is reset, and the carry signal 111 output from the flip-flop 6 is reset.
The flip-flop 8 is set via the input of (0), and the flip-flop 8 outputs the memory full signal 108 indicating the memory full state, and the internal bus A
It is sent to the transmission side via 201. On the transmitting side, upon receiving this memory full signal 108, it is confirmed that data transfer is impossible, and the subsequent data transfer is interrupted.

On the other hand, on the receiving side, first, the read address pointer / reset signal 105 is transferred to the internal bus B.
It is output to the FIFO 2 via 202. FI
In FO2, in response to the read address pointer reset signal 105, the read counter 7 is reset, whereby the status bit in the flip-flop 6 is set and the apparent memory full status is set. Next, a read completion signal 107 input from the receiving side
In response to this, the flip-flop 8 is reset, the memory full signal 108 is inverted and output, and it is transmitted to the transmitting side that all the memory cells are in the unreadable state, that is, the transmittable state. After that, the read signal 1 input from the receiving side
The data of the memory cells 5-1 to 5-n are sequentially read out via 06, and the read counter 7 is incremented each time the read signal 106 is input once, and the memory cells are sequentially designated. . When the data of the last memory cell is read, the flip-flop 6
The status bit at is reset and the carry signal 11
0 is output as 1 and is input to the flip-flop 8. As a result, the flip-flop 8 is set and the memory full signal 108 output from the flip-flop 8 is set.
Is 1 (memory full state) and is sent to the transmitting side. When the reading is completed in this state, the flip-flop 6 is reset via the read address pointer / reset signal 105 input from the receiving side, and the read completion signal 107 input from the receiving side is received. The flip-flop 8 is reset, and the memory full signal 108 is 0, that is, the information indicating the unreadable state is output. On the contrary, when the data is read again from the memory cell, the above-mentioned operation procedure is repeated from the beginning upon receiving the read address pointer / reset signal 105.

[0012]

As described above, according to the present invention, the transmitting side recognizes that the amount of data stored in the FIFO is in the limit value state, and the receiving side finally transmits the read completion signal. Since the data transfer is interrupted, the receiving side can reread the data any number of times during this period, and even if an unexpected situation occurs in the data transfer by the hardware, the control action of the sending side can be performed. Therefore, it is possible to take countermeasures on the receiving side without going through, and it is possible to improve the operating efficiency of the host processor on the transmitting side.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing an internal configuration of a FIFO in this embodiment.

FIG. 3 is a block diagram showing a conventional example.

[Explanation of symbols]

 1, 9 Host processor A 2, 10 FIFO 3, 11 Host processor B 4 Write counter 5-1 to 5-n Memory cell 6, 8 Flip-flop 7 Read counter

Claims (2)

[Claims] 1. A data communication device in which data is transferred via a FIFO, wherein a plurality of memory cells corresponding to a plurality of stages of buffers and a data write signal output from a transmission side are provided inside the FIFO. A write counter for generating and outputting a signal designating a memory cell to be written in the plurality of memory cells and a write signal for the designated memory cell, and sequentially transferring data to the plurality of memory cells. As the data is written, the first information holding means for holding the information indicating that the transfer data has been written in the final memory cell, and the plurality of the plurality of data corresponding to the data read signal output from the receiving side. Read counter that generates and outputs a signal designating a memory cell to be read out of the memory cells of and the read signal to the designated memory cell. If data communication apparatus characterized by comprising a second information holding means for holding information of the plurality of memory cells indicating whether all is readable. 2. The first and second information holding means,
The data communication device according to claim 1, each of which is formed by a flip-flop.