JPH0512072A - Computer fault information collection system - Google Patents

Abstract

(57) [Summary] [Purpose] Shorten the transfer time of the collected information. Configuration: Data representing the state of a computer system and its trace information are stored in RAM 15. RA
When collecting the contents of M15, the operation of the execution unit 4 of the computer system is stopped, the contents of the RAM 15 are frozen, and the contents of the RAM 15 are EEPR by the transfer unit 12.
Transfer to OM14. Then, the contents of the EEPROM 14 are sent to the printer and printed when the external device 22 such as the printer can be used for the operation of the system.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer fault information collecting system for storing data representing the state of a computer system and its trace information in a computer system and outputting the trace information when necessary.

[0002]

2. Description of the Related Art Conventionally, in order to analyze a fault in a computer system, data representing the state of the computer system and its trace information are stored and the fault information is collected by printing or the like when necessary. The system is being used.

FIG. 2 is a block diagram showing an example of a conventional computer fault information collection system. The fault information collecting system shown in this figure is a system for collecting fault information in a computer system for controlling peripheral devices connected to a central processing unit (hereinafter referred to as CPU) 19 of a host. This fault information collecting system is a random access storage device that stores data representing the state of a computer system, that is, program addresses, register contents, and the like, and trace information that sequentially records the data.
A memory (hereinafter, referred to as RAM) 15, a program storage unit 8 including a read only memory (hereinafter, referred to as ROM), a logic unit 20 connected to the RAM 15 and the program storage unit 8, and An external device 22 such as a printer connected to the logic unit 20 is provided. The CPU 19 of the host is connected to the logic unit 20.

The logic unit 20 includes a memory control unit 2 connected to the RAM 15, an execution unit 4 connected to the memory control unit 2 and the program storage unit 8, and the execution unit 4 and CP.
An external input / output unit 5 for inputting / outputting signals between the U 19 and the external device 22 and an address operation unit 7 connected to the execution unit 4 are provided. A RAM section input / output signal 51 is input / output between the RAM 15 and the memory control section 2, a memory input / output signal 52 is input / output between the memory control section 2 and the execution section 4, and the execution section 4 and the external input / output section are input. 5, an external input / output signal 53 is input / output between the external input / output unit 5 and the CPU 1.
9, external input / output signal 5 between external device 22
4. An external device input / output signal 55 is input / output.

The program storage unit 8 stores operation instructions, input / output instructions, and comparison instructions. The execution unit 4 fetches the instruction 56 from the program storage unit 8, and if it is a computation instruction, fetches the computation data from the RAM 15 via the memory control unit 2 and stores the computation result in the RAM 15 again. If the instruction 56 fetched from the program storage unit 8 is an input / output instruction, the execution unit 4 transfers data between the RAM 15 and the external input / output unit 5. Also, the execution unit 4
If the instruction 56 fetched from the program storage unit 8 is a comparison instruction, the comparison data is fetched from the RAM 15 and the comparison result is stored in the RAM 15. When the execution of one instruction is completed, the execution unit 4 outputs an instruction fetch request 57 to the address operation unit 7 to fetch the next instruction. When the execution stop interrupt 58 is detected, the execution of the instruction is stopped.

Further, the fault information collecting system further comprises:
A stop address setting switch 18 for setting an address of a portion where the operation of the execution unit 4 is desired to be stopped, a switch address register 17 for storing the address set by the stop address setting switch 18, and an execution unit 4
Program execution address register 9 that stores the address of the instruction that is being executed, and stop address register 1
7 and the content of the program execution address register 9 are compared and if they match, a comparison unit 16 that outputs an address match signal 61, and an execution unit 4 when the address match signal 61 from this comparison unit 16 is input And an interrupt control unit 21 for outputting an execution stop interrupt 58. A stop address setting signal 62 is sent from the stop address setting switch 18 to the stop address register 17, and a stop address 63 is sent from the stop address register 17 to the comparison unit 16. The program execution address register 9 sends the read address 64 to the program storage unit 8 and the execution address 65 to the comparison unit 16. Further, the program execution address register 9 sends out the arithmetic address 66 to the address arithmetic unit 7 of the logic unit 20 and inputs the calculated address 67 from the address arithmetic unit 7.

Next, the operation of the computer fault information collecting system will be described. The execution unit 4 fetches the instruction 56 from the program storage unit 8, performs an operation according to the type of the instruction, and when the execution is completed, issues an instruction fetch request 57 to fetch the next instruction to fetch the instruction fetch request 57.
Output to. The address arithmetic unit 7 takes out the arithmetic address 66 from the program execution address register 9 and performs arithmetic operation, and sequentially outputs the calculated address 67. The calculated address 67 is temporarily stored in the program execution address register 9 and then output to the program storage unit 8.

When it is desired to collect the contents of the RAM 15 when the execution unit 4 is executing the address of an instruction, the stop address setting switch 18 is used to set the address to be collected. The set address is temporarily held in the stop address register 17 by the stop address setting signal 62. The comparator 16 compares the stop address 63 from the stop address register 17 with the execution address 65 from the program execution address register 9 and outputs an address match signal 61 if they match. The interrupt control unit 21 which receives the address match signal 61
Outputs an execution stop interrupt 58 to stop the operation of the execution unit 4.

In this way, the operation of the execution unit 4 is stopped and R
Freeze the contents of AM15, that is, fix it, then CP
The contents of the RAM 15 are read out by U19, sent from the external input / output unit 5 to the external device 22, for example, a printer, and printed there.

[0010]

As described above, in the conventional computer fault information collecting system, the operation of the execution unit 4 is stopped in order to collect the contents of the RAM 15, the processing being executed is interrupted, and the external printer is stopped. The system was such that the contents of the RAM 15 were output.

However, it takes time to output the contents of the RAM 15 to the printer, and the CPU 19
Since the response in the input / output operation with and cannot be returned, C
There is a problem that the PU 19 may be logically disconnected.

Further, conventionally, the RAM 1 is provided between the printer and the printer.
Since there is no particular means for notifying that the output of the contents of 5 has been completed, there is a problem that it is not known when to restart the execution of the execution unit 4.

Therefore, a first object of the present invention is to provide a fault information collection system for a computer which can shorten the transfer time of information to be collected.

A second object of the present invention is, in addition to the above objects,
Another object of the present invention is to provide a computer fault information collection system that enables the user to know when to resume execution after the transfer of information to be collected.

[0015]

According to a first aspect of the present invention, there is provided a computer fault information collecting system including: a first memory for storing data representing a state of the computer system and trace information thereof; and at least a first memory. A non-volatile second memory having the same capacity and an operation stopping means for stopping the operation of the execution part of the computer system and freezing the contents of the first memory at a predetermined address, and the operation stopping means. The transfer means transfers the contents of the first memory frozen by the second memory to the second memory, and the output device outputs the contents of the second memory to an external device.

In this computer fault information collecting system, data representing the state of the computer system and its trace information are stored in the first memory. When the operation of the execution unit of the computer system is stopped by the operation stopping unit and the contents of the first memory are frozen, the contents of the first memory are transferred to the second memory by the transfer unit. Then, the contents of the second memory are output to the external device by the output means.

According to a second aspect of the invention, in the computer fault information collecting system of the first aspect, the transfer means sends a transfer end signal indicating the end of transfer to the operation stopping means when the transfer is completed, The operation stopping means outputs a signal for instructing the execution unit to restart the operation when receiving the transfer end signal.

In this computer fault information collecting system, when the transfer of the contents of the first memory to the second memory is completed, a transfer end signal is sent from the transfer means to the operation stop means, and the operation stop means is When the transfer end signal is received, a signal for instructing the operation unit to restart the operation is output. Therefore, the operation of the execution unit is restarted immediately after the transfer is completed.

According to a third aspect of the present invention, there is provided a computer fault information collecting system according to the first or second aspect, wherein an electrically erasable / writable read-only memory is used as the second memory. Is.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a computer fault information collection system according to an embodiment of the present invention.

The computer fault information collecting system of the present embodiment has a RAM 15 for storing data representing the state of the computer system and its trace information, and an electrically erasable / writable read having the same capacity as the RAM 15.・ Only Memory (Electic
all Erasable Programmable
e Read Only Memory: EEP
It is written as ROM. ) 14, a program storage unit 8 including a ROM, a logic unit 1 connected to the program storage unit 8, and an external device 22 such as a printer connected to the logic unit 1. The CPU 19 of the host is included in the logic unit 1.
Are connected.

The logic unit 1 includes a memory control unit 2, an input / output selection unit 3 connected to the memory control unit 2, and an execution unit 4 connected to the memory control unit 2 and the program storage unit 8.
An external input / output unit 5 for inputting / outputting signals between the execution unit 4, the CPU 19 and the external device 22, and an address calculation unit 7 connected to the execution unit 4.

The RAM 15 is connected to the input / output selection unit 3 of the logic unit 1 via the RAM input / output control unit 11, and EEPRO
The M14 is connected to the input / output selection unit 3 via the EEPROM input / output control unit 13. The RAM input / output control unit 11 and the EEPROM input / output control unit 13 are connected via the transfer unit 12.

A RAM input / output signal 71 is input / output between the RAM 15 and the RAM input / output control unit 11, and EEPRO
EE is provided between the M14 and the EEPROM input / output control unit 13.
The PROM input / output signal 72 is input / output, the RAM section input / output signal 51 is input / output between the RAM input / output control section 11 and the input / output selection section 3, and from the EEPROM input / output control section 13 to the input / output selection section 3. The EEPROM read signal 73 is transmitted. In addition, the RAM input / output control unit 11 to the transfer unit 12
The transfer read data 74 is sent to the
The transfer write data 75 is transferred to the EPROM input / output control unit 13. Further, the storage unit input / output signal 76 is input / output between the input / output selection unit 3 and the memory control unit 2, and the memory input / output signal 52 is input / output between the memory control unit 2 and the execution unit 4. An external input / output signal 53 is input / output between the unit 4 and the external input / output unit 5, and the external input / output unit 5 and the CPU 1
9, external input / output signal 5 between external device 22
4. An external device input / output signal 55 is input / output.

The RAM input / output control unit 11 detects the RAM save signal 77 from the transfer unit 12 to detect the RAM1.
The switching of the input / output signal to 5 and the saving of the contents of the RAM 15 are started. Further, the EEPROM input / output control unit 13
By detecting the EEPROM write signal 78 from the transfer unit 12, switching of input / output signals to the EEPROM 14 and writing to the EEPROM 14 are started. Also,
The transfer unit 12 stores the final address of the RAM 15,
RAM when the address match signal 61 from the comparison unit 16 comes
Data transfer from 15 to the EEPROM 14 is started, and when the data transfer is completed, a transfer end signal 79 is output.

The program storage unit 8 stores operation instructions, input / output instructions, and comparison instructions. The execution unit 4 fetches the instruction 56 from the program storage unit 8, and if it is an operation instruction, RA via the memory control unit 2 and the input / output selection unit 3.
The calculation data is taken out from M15 and the calculation result is again stored in the RAM.
15, the data is transferred between the RAM 15 and the external input / output unit 5 if it is an input / output command, and R if it is a comparison command.
The comparison data is retrieved from AM15 and the comparison result is stored in RAM1.
Store in 5. When the execution of one instruction is completed, the execution unit 4 outputs an instruction fetch request 57 to the address operation unit 7 to fetch the next instruction. When the execution stop interrupt 58 is detected, the execution of the instruction is stopped. The input / output selection unit 3 inputs / outputs data to / from the execution unit 4 from the RAM 15 or EE.
The PROM 14 is switched.

The fault information collecting system further comprises:
Similar to the system shown in FIG. 2, a stop address setting switch 18, a stop address register 17, a program execution address register 9, a comparison unit 16, and an interrupt control unit 6 are provided. Of these, the configuration excluding the interrupt control unit 6 is similar to that of the system shown in FIG. The interrupt control unit 6 in this embodiment includes a comparison unit 16
When the address match signal 61 from the execution unit 4 is input, the execution stop interrupt 58 is output to the execution unit 4, and when the transfer end signal 79 from the transfer unit 12 is detected, it is executed to the execution unit 4. The restart interrupt 80 is output.

Next, the operation of this embodiment will be described.
The comparison unit 16 uses the stop address 63 and the execution address 6
5 is compared, and if they match, an address match signal 61 is output. When the transfer unit 12 detects the address match signal 61, it outputs the RAM save signal 77 and the EEPROM write signal 78, and the RAM input / output control unit 11 and the EE.
The PROM input / output control unit 13 is caused to start data transfer. Then, the transfer unit 12 includes the RAM input / output control unit 11
The operation of receiving the transfer read data 74 sent from the device and outputting it as the transfer write data 75 to the EEPROM input / output control unit 13 is repeated until the total number of transfer bytes becomes the same as the capacity of the RAM 15. The total number of bytes transferred is RAM
When the capacity of 15 is reached, the transfer unit 12 suppresses the output of the RAM save signal 77 and the EEPROM write signal 78, and outputs the transfer end signal 79. When detecting the transfer end signal 79, the interrupt control unit 6 sends an execution restart interrupt 80 to the execution unit 4 to restart the operation of the execution unit 4.

On the other hand, the RAM input / output control unit 11 is a RAM
When the save signal 77 is detected, the input / output signal 71 to / from the RAM 15 is switched from the RAM section input / output signal 51 to the transfer read data 74, and the contents of the RAM 15 are sequentially transmitted as the transfer read data 74 from the youngest address. When the RAM save signal 77 is not detected, the transmission of the transfer read data 74 is stopped, and the input / output signal 71 is switched from the transfer read data 74 to the RAM section input / output signal 51.

The EEPROM input / output control unit 13 is
If the EEPROM write signal 78 is detected, the EEPR
Input / output signal 72 to / from OM14 is EEPROM read signal 7
3 is switched to the transfer write data 75, and the contents sent as the transfer write data 75 are sequentially stored from the youngest address of the EEPROM 14. And EEP
When the ROM write signal 78 is not detected, the transfer write data 75 is stopped to be fetched and the input / output signal 72 is switched from the transfer write data 75 to the EEPROM read signal 73.

The contents stored in the EEPROM 14 are sent from the external input / output unit 5 to the external device 22, for example, a printer, and printed there when the external device 22 such as, for example, a printer can be used in operation of the system. .

The other operations are similar to those of the system shown in FIG.

As described above, according to this embodiment, the RAM 15
Since the EEPROM 14 is provided for saving the data stored in the RAM 15 and the contents of the RAM 15 are transferred to the EEPROM 14, the transfer time of the data stored in the RAM 15 is shortened and the CPU 19 is logically disconnected during the transfer. Will disappear.

Further, according to this embodiment, after the transfer of the contents of the RAM 15 is completed, the transfer unit 12 sends a transfer end signal 79 to the interrupt control unit 6, and in response to this, the interrupt control unit 6 executes the execution unit 4. Since the execution restart interrupt 80 is sent to the RAM,
The operation of the execution unit 4 can be restarted immediately after the transfer of the contents of 15 is completed.

Further, according to the present embodiment, the EEPROM 1
The contents stored in 4 are stored in the external device 2 in the operation of the system.
2. Since it is possible to send the data to the printer for printing when it is sufficient to use the printer, for example, it is possible to collect the fault information without interrupting the processing even during system operation.

[0036]

As described above, according to the first or third aspect of the invention, the information collected in the first memory is stored in the second memory.
Since the data is transferred to the second memory and output from the second memory to the external device, there is an effect that the transfer time of the information to be collected can be shortened.

According to the invention of claim 2 or 3, when the transfer of the contents of the first memory to the second memory is completed, the transfer means sends a transfer end signal to the operation stopping means. As a result, in addition to the above effects, there is an effect that it is possible to know the execution restart time after the transfer of the information to be collected is completed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a computer fault information collection system according to an embodiment of the present invention.

FIG. 2 is a block diagram showing an example of a conventional computer fault information collection system.

[Explanation of symbols]

1 logic 4 execution section 6 Interrupt control section 11 RAM input / output control unit 12 Transfer unit 13 EEPROM input / output control unit 14 EEPROM 15 RAM 19 CPU 22 External device

Claims (3)

[Claims] 1. A first memory for storing data representing the state of a computer system and its trace information, a non-volatile second memory having at least the same capacity as the first memory, and a predetermined memory. At the address, the operation of the execution unit of the computer system is stopped and the contents of the first memory are frozen, and the contents of the first memory frozen by the operations halting unit are stored in the second memory. A fault information collecting system for a computer, comprising: a transfer unit for transferring the contents of the second memory to an external device; and an output unit for outputting the contents of the second memory to an external device. 2. The transfer means sends a transfer end signal indicating the end of transfer to the operation stopping means when the transfer is completed, and the operation stopping means operates on the execution unit when receiving the transfer end signal. 2. The fault information collection system for a computer according to claim 1, wherein a signal for instructing resumption is output. 3. The fault information collecting system for a computer according to claim 1, wherein the second memory is an electrically erasable / writable read-only memory.