JPH05121291A - Method and apparatus for reduced projection - Google Patents

Abstract

(57) [Abstract] [PROBLEMS] To provide a method and apparatus for reducing projection exposure of a fine pattern, which is used in semiconductor device manufacturing or the like, and provides a reduction projection exposure method that facilitates pattern formation with high integration and high resolution. With the goal. In a reduction projection exposure method in which light transmitted through a mask is reduced and projected by an optical system to transfer a pattern image onto a semiconductor wafer or a reticle, the mask is capable of changing the light transmittance according to an external signal. It is characterized in that different pattern images are reduced and projected onto the semiconductor wafer or reticle a plurality of times with the mask element and the semiconductor wafer or reticle fixed while including the index element.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to projection exposure, and more particularly to a method and apparatus for reducing projection exposure of a fine pattern used in semiconductor device manufacturing and the like.

In recent years, as the degree of integration of semiconductor integrated circuit devices has improved, the cell size of semiconductor devices used in semiconductor integrated circuit devices has continued to decrease. The minimum pattern size required approaches the resolution limit of light.

[0003]

2. Description of the Related Art In conventional reduction projection exposure, a pattern image is obtained by reducing and projecting light transmitted through a mask having a desired pattern onto a semiconductor wafer or reticle. The mask is, for example, Cr on a quartz substrate.
It is constituted by forming a pattern of the film.

When the desired pattern image cannot be obtained due to the aberration of the optical system or the like, the desired pattern image is obtained by forming a Cr pattern in which the aberration is corrected. The pattern of such a mask is fixed, and when changing the pattern, another mask was created and used.

The light transmitted through the mask having the pattern of the light-shielding film changes its shape by diffraction and interference. That is, due to diffraction, the light wraps around to the shadow,
Interference occurs when light and light are polymerized.

As the degree of integration and miniaturization of semiconductor integrated circuits increases, individual patterns in a mask are miniaturized, and the distance between patterns is reduced. When the transmitted light patterns come close to each other, the resolution limit of the projection optical system is λ / NA.
A transmitted light pattern having a wavelength (λ is an exposure wavelength and NA is a numerical aperture of a projection lens) is less than the light intensity contrast,
Resolution becomes difficult.

Even if the image can be resolved, since the image intensity contrast is low, it becomes difficult to control the pattern width on the image plane, and it is extremely difficult to obtain a desired pattern size.
Similar problems occur not only when the distance between adjacent transmitted light patterns decreases, but also when the size of a single transmitted light pattern decreases.

Further, when a mask for forming a desired pattern is prepared, and a pattern image is actually produced by reduction projection, an image which is significantly different from the desired pattern can be obtained due to the influence of light diffraction and interference. There is also.

In such a case, it is necessary to correct the pattern on the mask in advance. However, there is a limit to the correction pattern that can be incorporated in the one-layer mask pattern, and it is difficult to cope with arbitrary pattern correction.

Various structures are formed on a semiconductor wafer, and a step is generated. In the stepped portion, there is a problem that the pattern shape is distorted due to the influence of reflected light or the like. Conventionally, measures such as forming an antireflection film on a semiconductor wafer and incorporating a dye into a photoresist to absorb scattered light have been taken.

However, these measures impose a heavy load on the wafer process and hinder the adoption of a high step structure for device design. Alternatively, the pattern width can be changed in advance. In this case, it was necessary to remake the mask until an appropriate pattern was obtained.

Further, as the chip size increases, the exposure area (shot size) tends to increase. However, as the NA of the projection lens increases, it becomes difficult to suppress the aberration in a wide shot area. Aberration causes deterioration of pattern accuracy.

Further, as the pattern size becomes finer, it becomes difficult to manufacture the mask itself.
In order to supply defect-free masks over the entire area, the burden on the manufacturing process, inspection process, and repair process becomes large, and it is necessary to remake many times to obtain a complete product, resulting in a lot of cost and time. Is consumed.

[0014]

As described above,
According to the reduction projection exposure technique using the conventional fixed mask,
It becomes increasingly difficult to create high-resolution patterns with improved integration.

An object of the present invention is to provide a reduction projection exposure method which facilitates pattern formation with high integration and high resolution. Another object of the present invention is to provide a reduction projection exposure apparatus that facilitates pattern formation with high integration and high resolution.

[0016]

The reduction projection exposure method of the present invention is a reduction projection exposure method for reducing and projecting light transmitted through a mask by an optical system to transfer a pattern image onto a semiconductor wafer or reticle. Includes a large number of variable transmittance elements that can change the light transmittance according to an external signal, and reduces and projects different pattern images a plurality of times on the semiconductor wafer or reticle with the mask and the semiconductor wafer or reticle fixed. To do.

[0017]

Since the mask includes a large number of variable transmittance elements that can change the light transmittance according to an external signal, a different number of different pattern images can be reduced and projected without changing the relative relationship between the mask and the semiconductor wafer or reticle. be able to.

If the pattern images to be created are close to each other and the desired resolution or the like cannot be obtained due to the diffraction and interference of light when projected at the same time, the pattern images to be created are decomposed,
It is possible to avoid light interference by separately performing the reduced projection.

When a fine pattern such as a contact hole is exposed, a plurality of elongated patterns are crossed and exposed separately, so that a pattern with high dimensional accuracy can be exposed.

[0020]

1 shows a reduction projection exposure apparatus according to an embodiment of the present invention. The light emitted from the light source 1 is directly or reflected by the reflecting mirror 2 and enters the condenser lens 3.
The light emitted from the condenser lens 3 illuminates the mask substrate 4. A large number of variable transmittance elements 5 are formed on the mask substrate 4, and these variable transmittance elements 5 change their transmittance according to the signals supplied from the signal lines 7 and 8.

The light selectively transmitted through the mask substrate 4 is converged by the projection lens 9 and imaged on the semiconductor wafer 12 placed on the stage 11. The projection lens 9
Light projected onto the semiconductor wafer 12 from the shutter 1
The passage is controlled by 0.

The pattern to be drawn is sent from the pattern data generator 15 to the pattern data storage device 14 and stored therein. The pattern data read from the pattern data storage device 14 is supplied to the controller 13,
Its composition is analyzed.

The controller 13 forms a plurality of divided patterns for generating a desired pattern as a whole, and supplies a control signal 20 for realizing the pattern to the mask substrate 4.

If the pattern projected on the semiconductor wafer 12 is different from the desired pattern, the correction data generator 16 supplies the correction data to the controller 13, and the controller 13 creates the pattern information in which the difference is corrected. Then, the control signal 20 is supplied to the mask substrate 4.

The mask substrate 4 has a large number of variable transmittance elements 5
Is formed, and each element 5 changes its transmittance by the control signal 20. Therefore, an arbitrary pattern can be formed by the control signal 20.

For example, patterns 21 and 22 to be created
Are close to each other, and when the two patterns 21 and 22 cannot be separated due to diffraction and interference of light when exposed at the same time, the controller 13 sets the patterns 21 and 22 as separate patterns and exposes them at different timings. Two adjacent patterns can be exposed without light interference.

At this time, the mask substrate 4 and the semiconductor wafer 12
Since a plurality of patterns can be exposed while the relative relationship of is fixed, position accuracy does not deteriorate. In this way, by exposing a plurality of patterns without changing the position of the mask with respect to the semiconductor wafer or reticle, it is possible to expose a highly accurate pattern that prevents light interference.

A more specific embodiment of the present invention will be described below. FIG. 2 is a diagram illustrating a reduction projection exposure method according to an embodiment of the present invention. As shown in FIG. 2 (A),
Consider the case where a plurality of lines 23, 24, 25, 26 expose patterns in close proximity. According to the conventional technique, a pattern having a magnification corresponding to the reduction ratio of the reduction projection exposure system is created, and reduction projection exposure is performed to create such a pattern. For example, a Cr mask 28 having openings in the lines 23 to 26 is formed and projected on the wafer.

However, the line pattern period is λ / N.
When the resolution becomes smaller than the resolution limit determined by A, the light intensity projected due to diffraction and interference of light becomes as shown by the curve 30, and the image contrast decreases.

Therefore, as the distance between lines decreases, it becomes more difficult to resolve adjacent lines. When exposing a proximity pattern exceeding such a resolution limit, the pattern to be exposed is decomposed and a plurality of masks as shown in FIGS. 2B and 2C are created.

The first mask shown in FIG. 2B is composed of a light shielding pattern 32 having openings at the first line 23 and the third line 25. The spacing between lines 23 and 25 is chosen to be greater than the resolution limit λ / NA.

The second mask shown in FIG. 2C is
It is formed by a light-shielding pattern 35 having openings in the portions of the second line 24 and the fourth line 26. These openings and light-shielding patterns can be created by controlling the mask substrate 4 shown in FIG.

The first mask shown in FIG. 2B and FIG.
The second mask shown in (C) has line patterns separated by a distance greater than the resolution limit, respectively, to create a clearly resolved image pattern, as shown by curves 33 and 36, respectively. Since the image patterns 33 and 36 are exposed separately, there is no interference between the lights. The total exposure dose received by the photoresist on the semiconductor wafer is as shown in FIG.

In FIG. 2D, adjacent peaks are exposed at different times, so that they do not interfere with each other. Therefore, a pattern having high contrast and resolution is easily exposed. Also, the pattern width is prevented from changing due to interference.

FIG. 3 shows another embodiment of the present invention. Figure 3
As shown in (A), consider the case where a grid pattern having a pattern period of 0.6 μm and a space width of 0.3 μm is created. According to the conventional technique, the light shielding portions 41, 42, 43, 44
Create a mask formed of light-shielding parts that are adjacent to each other,
When the reduced projection exposure is performed, the intensity distribution of the light radiated on the semiconductor wafer becomes a curve 45.

I-line with exposure wavelength of mercury (λ = 365 nm)
The numerical aperture of the lens is NA = 0.5, the coherence coefficient is σ = 0.5, and the reduction ratio is ⅕. At this time, the resolution λ / NA of the exposure apparatus is λ / NA = 0.7
3 μm, which is larger than the pattern period of 0.6 μm.
Therefore, the light intensity distribution on the semiconductor wafer rises even in the light-shielding portion as shown by the curve 45, the contrast is low, and resolution becomes difficult.

In this embodiment, since the pattern as shown in FIG. 3A is exposed, the pattern 2 shown in FIG.
Use different types of masks. In the mask on the left side of FIG. 3B, only the opening 48 between the light shielding portions 42 and 43 and the outer peripheral opening are formed, and the opening 49 between the light shielding portions 41 and 42 and between the light shielding portions 43 and 44. The opening 50 is removed and the light shielding portions 46 and 47 are formed.

Therefore, light-shielding portions 46 and 47 having a width of 0.9 μm are formed between the central opening 48 having a line width of 0.3 μm and the outer opening. Therefore, these openings are well resolved as shown by curve 52.

In the mask on the right side of FIG. 3B, only the openings 49 and 50 are formed. The distance between these openings is 0.9 μm, which is also sufficiently larger than the resolution. Thus, the projected light intensity is well resolved into two lines, as shown by curve 54.

These two masks are formed following the mask having the variable transmittance element, and are separately projected onto the semiconductor wafer to obtain an exposure intensity pattern 56 as shown in FIG. 3C. Since the adjacent peaks are projected separately, light interference is prevented and resolution is possible.

FIG. 4 shows a case where an isolated pattern such as a contact hole is formed according to an embodiment of the present invention. In order to expose the isolated pattern, according to the conventional technique, for example, a light shielding mask 59 having an opening 58 as shown in FIG.

However, when the pattern width is smaller than the resolution λ / NA, the projected light intensity 60 becomes wider than the pattern width to be created, the contrast is lowered, and the resolution becomes difficult.

In such a case, a plurality of intersecting rectangular patterns 62 and 63 are used as shown in FIG.
The desired pattern is obtained by developing only the overexposed areas.

In the illustrated configuration, the vertically long pattern 6
The light intensity distributions 64 and 65 are separately created by creating 2 and a horizontally long pattern 63 and successively exposing. Since the contrast of the image formed by the rectangular pattern is higher than that of the hole pattern, the light intensity contrast obtained by combining the two becomes high as shown in FIG. 4C, and it becomes possible to form a fine hole pattern.

In this way, when performing overexposure,
It is chosen so that the required exposure intensity is achieved in the overexposed areas and that the areas of only one exposure are not developed. For example, the exposure of each of the patterns 62 and 63 is performed with 1/2 of the exposure amount of the conventional mask.

FIG. 5 shows another embodiment of the present invention. Figure 5
As shown in (A), consider the case of forming a hole pattern having a width of about 0.4 μm. According to the conventional technique, since the pattern width 0.4 μm is smaller than the resolution 0.73 μm, the contrast becomes low and it becomes difficult to resolve.

In this embodiment, as shown in FIG. 5B, elongated patterns 67, 68 and 69 each having a pattern width of 0.4 μm and rotated by 45 ° are overlaid and exposed. Each exposure is performed with a light intensity of 1/3 of the conventional exposure amount.

In this way, after the triple exposure, the line pattern 6 can be obtained by developing only the area exposed three times.
Only the common portion of 7, 68 and 69 is developed to form a pattern 70 having a sharp light intensity distribution. As the length of each pattern is increased, the contrast at the center is improved, and resolution is facilitated.

FIG. 6 shows another embodiment of the present invention. Figure 6
Consider a case where a pattern in which a vertical line pattern 71 and a horizontal line pattern 72 intersect as shown in FIG.

When this cross line pattern is exposed as it is by the conventional technique, as shown on the right side of FIG. 6A, the light intensity 74 at the intersection 73 becomes high, and the shadowed portions 75 to 78 are formed. The corners are removed and the rounded pattern is developed.

Therefore, as shown in FIG. 6B, two masks which are divided by removing the intersecting portion are formed and separated and exposed. The first mask shown on the left side of FIG.
The vertical pattern 71a and the horizontal pattern 72a except for 3 and its vicinity are included. By performing exposure with such an opening pattern, it is possible to prevent the formation of the central region 74 having high light intensity.

However, since the light intensity becomes too low at the intersection 73, the overexposure is performed with the second pattern having the opening pattern 73a corresponding to the intersection 73. The size of the aperture 73a does not have to be the same as that of the intersection 73, and it is sufficient to compensate for the insufficient light intensity. In the illustrated configuration, the opening pattern 73a is the intersection 73
Created somewhat smaller than the size of.

Overlapping exposure is performed using such two masks to develop a cross pattern as shown in FIG. 6C. By adjusting the dimensions of the openings 71a, 72a, 73a without interference between the light exposed by the two masks, it is possible to obtain a good pattern in which the bulge at the intersection is suppressed.

FIG. 7 shows another embodiment of the present invention. Figure 7
(A) As shown on the left side, consider the case where a pattern having a line-shaped shadow 82 is exposed on a base surface having a step portion 81. The step portion is formed by various structures formed on the semiconductor wafer, and the reflectance is often different from that of the peripheral portion.

In such a case, if the pattern having a line-shaped shadow portion is exposed as it is by the conventional technique, a twist 83 is generated at the stepped portion 81 as shown at 83 in FIG. 7A. There is.

To correct such a twist, FIG.
(B) As shown on the left side, the portion 8 bulged by the step 81
4 may be formed. In this case, according to the conventional technique, another mask having a bulge 84 is created from the beginning so as to correct the swelling 83, exposed and developed, and the result is inspected. Had to remake the mask again.

When the mask substrate 4 including a large number of variable transmittance elements 5 as shown in FIG. 1 is used, it is not necessary to remake the mask substrate, and the exposure by the correction pattern is realized only by converting the input data. can do. By using the data corrected in this way, FIG.
(B) As shown on the right side, it is possible to obtain an exposure pattern in which the distortion is corrected.

When a reduction optical system using a lens or the like is used,
Aberration peculiar to the lens occurs. In order to correct the aberration caused by such an optical system, the mask pattern may be corrected in advance in consideration of the aberration. In this case as well, conventionally, the mask substrate had to be recreated from the beginning, and it was not easy to correct the aberration in terms of cost and time.

If a projection exposure system as shown in FIG. 1 is used,
It is possible to correct the aberration by correcting the pattern shape of the mask simply by creating the necessary correction data. Therefore, the cost and time required for mask production and inspection are saved.

FIG. 8 shows an example of the structure of the variable transmittance element 5 shown in FIG. As shown in FIG. 8A, a liquid crystal cell 88 containing a twisted nematic liquid crystal is arranged between a pair of substrates having transparent electrodes between a pair of orthogonal polarizers 87 and 89. The incident light transmitted through the polarizer 87 becomes linearly polarized light which is polarized in the polarization direction P1 of the polarizer 87.

The polarization direction of this polarized light is rotated by about 90 ° by the twisted nematic liquid crystal when no voltage is applied to the liquid crystal cell 88. The incident light whose polarization direction is rotated matches the polarization direction of the exit-side polarizer (analyzer), and exits as it is.

When a voltage is applied to the liquid crystal cell, the liquid crystal molecules are aligned in the direction of the electric field and lose the function of rotating the polarization direction of incident light. Therefore, the linearly polarized light that has passed through the polarizer 87 is incident on the exit side polarizer 89 without rotating the polarization direction. Since the polarization axis P2 of the exit side polarizer 89 is orthogonal to the polarization axis P1 of the entrance side polarizer, the incident light is blocked and the exit light is almost zero.

In this way, a variable transmittance element whose light transmittance can be controlled by an external signal is provided. Figure 9
Substrate mask 4 using variable transmittance elements as shown in FIG.
A configuration example of is shown. FIG. 9A is a perspective view schematically showing the entire structure, and FIG. 9B is an equivalent circuit of a liquid crystal cell.

As shown in FIG. 9A, one glass substrate 91 provided with a transparent electrode 92 for forming a large number of liquid crystal cells between a pair of orthogonal polarizers 87 and 89, and a liquid crystal layer 9.
3. The other glass substrate 95 having a large number of selectively driven transparent electrodes is sandwiched. On the glass substrate 95, the scanning lines 96 arranged in the horizontal direction and the signal lines 97 arranged in the vertical direction are arranged, and the intersections form a matrix.

At each element of the matrix, a transparent electrode 101 and a thin film transistor (TFT) 102 for controlling the voltage applied to the transparent electrode 101 are arranged. By controlling the voltage of the scanning line 96, the applied voltage of the signal line 97 is applied to the transparent electrode 101, and the alignment of the liquid crystal 93 sandwiched between the transparent electrode 92 and the transparent electrode 92 is controlled.

The area of each liquid crystal cell is, for example, 0.5 to
The area is 0.2 μm square. Arranging such liquid crystal cells in a large number of substrate masks makes it possible to create an arbitrary pattern by a control signal. The structure of this liquid crystal mask is similar to the active matrix used in the liquid crystal display panel.

FIG. 9B shows an equivalent circuit of each cell. 1
The pixel operation includes a writing operation and a holding operation. When the thin film transistor 102 is turned on, the capacitance unit C1,
The voltage of the signal line 97 is applied to C2. The capacity C1
Indicates the capacitance of the liquid crystal, and the capacitance C2 indicates the charge storage capacitance. The thin film transistor 102 is turned on / off by the scanning line 9
6 signal.

When the thin film transistor 102 is turned on once and then turned off again, the written charges are stored in the charge storage capacitor C2, and a driving voltage is applied to the liquid crystal C1. The writing operation is performed for 10 to 20 μsec which is one scanning period, and the holding operation is continued for about 10 to 20 msec.

The thin film transistor is a CV on a glass substrate.
It is created using a thin film deposition technique by D or sputtering and a fine pattern formation technique by EB lithography. The gate wiring to be the scanning line is formed of, for example, aluminum, and the SiN film is used as the insulating film.

Further, ITO (indium tin oxide) or the like is used for the transparent electrode. Further, in order to prevent light leakage from the portion other than the transparent electrode, a light shielding layer is provided in the region other than the transparent electrode.

With this structure, a mask substrate on which an arbitrary pattern can be formed by an external signal is formed. Although the present invention has been described with reference to the embodiments, the present invention is not limited to these. For example, it will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

[0072]

As described above, according to the present invention,
Since it is possible to create an arbitrary pattern on the same mask substrate, it is possible to sequentially expose a plurality of patterns while fixing the relative position between the mask and the subject. By dividing the pattern to be exposed, light interference can be prevented and high resolution can be realized.

[Brief description of drawings]

FIG. 1 is a schematic perspective view showing an embodiment of the present invention.

FIG. 2 shows an embodiment of the present invention. 2A is a schematic diagram showing a reference technique, FIGS. 2B and 2C are schematic diagrams illustrating a mask pattern according to an embodiment of the present invention, and FIG. 2D is provided on a subject. It is a graph which shows distribution of total exposure intensity.

FIG. 3 shows an embodiment of the present invention. FIG. 3A is a schematic diagram for explaining the reference technique, FIG. 3B is a schematic diagram showing a plurality of mask patterns according to an embodiment of the present invention, and FIG. It is a graph which shows distribution of exposure intensity.

FIG. 4 shows an embodiment of the present invention. 4A is a schematic diagram for explaining the reference technique, FIG. 4B is a schematic diagram for explaining overlay exposure according to the embodiment of the present invention, and FIG. 4C is according to the embodiment of the present invention. It is a graph which shows the distribution of the given total exposure intensity.

FIG. 5 shows an embodiment of the present invention. FIG. 5A is a schematic diagram for explaining the reference technique, and FIG. 5B is a schematic diagram for explaining overlay exposure according to the embodiment of the present invention.

FIG. 6 shows an embodiment of the present invention. FIG. 6A is a schematic diagram for explaining the reference technique, FIG. 6B is a schematic diagram showing a split mask according to an embodiment of the present invention, and FIG. 6C is a composite formed by exposure of the split mask. It is a schematic plan view which shows an exposure area.

FIG. 7 shows an embodiment of the present invention. FIG. 7A is a schematic diagram showing the reference technique, and FIG. 7B is a schematic diagram for explaining the correction according to the embodiment of the present invention.

FIG. 8 is a conceptual diagram for explaining a variable transmittance element used in the configuration of FIG.

9 shows a substrate mask used in the configuration of FIG. Figure 9
FIG. 9A is a perspective view showing the configuration, and FIG. 9B is an equivalent circuit of a unit cell.

[Explanation of symbols]

 1 Light Source 2 Reflector 3 Condenser Lens 4 Mask Substrate 5 Variable Transmittance Element 7, 8 Signal Line 9 Projection Lens 10 Shutter 11 Stage 12 Wafer 13 Controller 14 Pattern Data Storage 15 Pattern Data Generator 16 Correction Data Generator 20 Control Signal

Claims (6)

[Claims] 1. A reduction projection exposure method in which light transmitted through a mask (4) is reduced and projected by an optical system (9) to transfer a pattern image onto a semiconductor wafer (12) or a reticle, wherein the mask (4) is It includes a large number of variable transmittance elements (5) whose light transmittance can be changed by an external signal (20), and reduces and projects different pattern images on the semiconductor wafer or reticle a plurality of times while fixing the mask and the semiconductor wafer or reticle. A reduced projection exposure method comprising: 2. The reduction projection exposure method according to claim 1, wherein the different pattern images have no common part. 3. The reduced projection exposure according to claim 1, wherein the different pattern images have a common portion, and the intensity of light to be reduced and projected is selected so as to satisfy a desired exposure intensity in the common portion to be overprinted. Method. 4. A light source fixed to a predetermined position to emit light, a mask fixed to a predetermined position and including a large number of variable transmittance elements for changing transmittance according to an applied signal, and a control signal applied to the mask. A reduction projection exposure apparatus including a control circuit and an optical system that reduces and projects the light transmitted through the mask onto an image plane to form a pattern image. 5. The reduction projection exposure apparatus according to claim 4, further comprising means for inputting pattern data and dividing the pattern data when the inter-pattern distance is equal to or less than a predetermined value. 6. The reduction projection exposure apparatus according to claim 4, further comprising correction means for inputting correction data based on the reduced-projection pattern image and correcting a control signal applied to the mask.