JPH0512175A - Peripheral controller - Google Patents

Abstract

PURPOSE:To improve the reliability of data without complicating a program by checking the port attribute through the hardware. CONSTITUTION:A main storage data attribute store part 1 has an address space equal to a main storage and stores the data showing the attribute of a port that shows the control information on a specific port showing the data stored in the main storage part. Then a main storage data attribute register 3 is added to transfer the data on the part 1 together with an attribute data register 4 which stores the port attribute value in a port control state based on a microprogram, and a comparator 5 which compares the value of the register 3 with the value of the register 4. In such a constitution, a peripheral controller performs the interruption control when the comparator 5 detects the inequality of the register values.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a peripheral control device, and more particularly to a peripheral control device which operates by vertical microprogram control.

[0002]

2. Description of the Related Art Conventionally, this type of peripheral control device has no means for individually identifying the attributes of individual data on a memory.
There was unlimited access.

[0003]

In this conventional peripheral control device, since the data on the memory can be accessed indefinitely, even if the data of the port other than the port to be controlled is erroneously read. , There was a possibility of malfunction because there is no function to check it.

Similarly, even if data is written in an area in which data of a port other than the port to be controlled is erroneously written, there is no function to check it, so that control data of other ports may be destroyed. was there.

[0005]

In a peripheral control device having a plurality of ports, the device of the present invention has the same address space as the main memory unit, and the port in which the data stored in the main memory unit is stored. A main memory data attribute storage unit that stores data indicating the port attribute indicating control information, a main memory data attribute register that transmits and receives data in the main memory data attribute storage unit, and a port is controlled by a microprogram. The attribute data register for storing the attribute value of the port, and a comparator for comparing the value of the main memory data attribute register with the value of the attribute data register when the mismatch is detected by the comparator. When it does, it is characterized in that interrupt control is performed.

[0006]

The present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the peripheral control device of the present invention.

This peripheral controller is provided with an instruction register 7, an address register 6, a main memory data attribute register 3, an attribute data register 4, a memory register 8, an accumulator 9, a port 21, a port 22, via an internal bus 13.
Ports 23 and 24 are connected to each other.

The address register 6 is connected to the main storage unit 2 and the main storage data attribute storage unit 1 via the address bus 14, and the main storage unit 2 is connected to the instruction register 7 and the memory register via the data bus 15. To be done. The main memory data attribute storage unit 1 is connected to the main memory data attribute register 3 via the data bus 16. Both the main memory data attribute register 3 and the attribute register 4 are input to the comparator 5, and the comparator 5 interrupts. Control device 11 via signal line 17
Connected to.

The instruction register 7 is also connected to the control unit 11, and the control unit 11 interprets the operation code of the instruction register. Memory register 8 and accumulator 9
Is connected to the arithmetic unit 10 and the result of the arithmetic operation in the arithmetic unit 10 is set in the accumulator 9.

FIG. 2 is a data storage image of the main storage unit 2 and the main storage data attribute storage unit 1, in which data and corresponding port attributes exist in pairs at the same address.

Next, the operation of the peripheral control device of this embodiment having the above-described structure will be described.

When the control device 11 controls the port 21, it selects the port 21 and at the same time, the attribute data register 4
Set the port attribute data to. First, consider a case where control data for controlling the port 21 is read from the main storage unit 2.

The control unit 11 includes a program counter 12
In accordance with the above, the micro instruction is read from the main storage unit 2 into the instruction register 7. The operation code of the microinstruction is set in the control device 11 and decoded to recognize that it is a memory read.

The control unit 11 sets the operand of the instruction register 7 in the address register 6 and sets the address bus 1
The corresponding addresses in the main storage unit 2 and the main storage data attribute storage unit 1 are selected via 4. Further, the data of the main storage unit 2 is set in the memory register 8 via the data bus 15, and the data of the main storage data attribute storage unit 1 is set in the main storage data attribute register 3 via the data bus 16.

The comparator 5 compares the already set value of the attribute data register 4 with the value of the main memory data attribute register 3, and if the attribute data match, the memory read process is completed. If the result of the comparator 5 does not match here, the interrupt processing of the program is controlled by the control device 11 via the interrupt signal line 17 and abnormal processing of data attribute mismatch is performed.

Next, consider a case where control data for controlling the port 21 is written from the accumulator 9 to the main memory 2.

The control unit 11 includes a program counter 12
In accordance with the above, the micro instruction is read from the main storage unit 2 into the instruction register 7. The operation code of the microinstruction is set in the control device 11 and decoded to recognize that it is a memory write. The operand of the instruction register is set in the address register 6, and the corresponding address in the main memory 2 and the main memory data attribute storage 1 is selected via the address bus 14. Data is transferred from the accumulator 9 to the memory register 8. Data in the main memory data attribute storage unit 1 is transferred via the data bus 16 to the main memory data attribute register 3
Set to.

The value of the attribute data register 4 which has already been set is compared with the value of the main memory data attribute register 3 by the comparator 5, and if the attribute data match, the data bus 1
The contents of the summary register 8 are set in the main memory 2 via 5, and the memory write process is completed. If the result of the comparator 5 does not match here, the controller 11 activates the interrupt processing of the program through the interrupt signal line 17, and the abnormal processing of the data attribute mismatch is performed.

[0020]

As described above, the present invention has the main memory data attribute storage unit in the same space as the main memory unit, and when the main memory unit is read or written, the port attribute value of the address is set. By comparing the value of the attribute data register with the hardware, it is possible to check whether or not the data corresponds to the port being controlled without being aware of it in the program. Therefore, the reliability of the data can be improved without complicating the program. There is an effect that can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a peripheral control device of the present invention.

FIG. 2 is a data storage image of a main storage unit and a main storage data attribute storage unit according to the present invention.

[Explanation of symbols]

 1 Main memory data attribute storage unit 2 Main memory unit 3 Main memory data attribute register 4 Attribute data register 5 Comparator 6 Address register 7 Instruction register 8 Memory register 9 Accumulator 10 Arithmetic unit 11 Controller 12 Program counter 13 Internal bus 14 Address bus 15, 16 Data bus 17 Interrupt signal line 21, 22, 23, 24 ports

Claims (1)

Claim: What is claimed is: 1. In a peripheral control device having a plurality of ports, which port has control information having the same address space as that of the main memory, and which data is stored in the main memory. A main memory data attribute storage unit that stores data indicating the attribute of the port that is represented, a main memory data attribute register that transmits and receives data in the main memory data attribute storage unit, and when controlling the port by the microprogram, An attribute data register for storing an attribute value of the port, and a comparator for comparing the value of the main memory data attribute register with the value of the attribute data register, and when the comparator detects a mismatch, an interrupt is generated. A peripheral control device characterized by performing control.