JPH05122020A - Static type transfer gate sequential circuit - Google Patents

Abstract

(57) [Summary] [Object] To provide a static transfer gate sequential circuit capable of high-speed operation equivalent to that of a dynamic type and capable of coping with low-speed operation. [Structure] A transfer gate TG, two inverters V1 and V2, an input terminal D, an output terminal QB, and a clock input terminal CC are provided. One end of the transfer gate TG is connected to the input terminal D to separate the transfer gate TG. To the input terminal of the inverter V1
Is connected to the output terminal QB and the input terminal of the inverter V2, and the output terminal of the inverter V2 is connected to the input terminal of the inverter V1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sequential circuit such as a latch circuit, a frequency divider and a prescaler which operates at high speed.

[0002]

2. Description of the Related Art Any sequential circuit is constructed by combining basic latch circuits. When the latch circuit is constructed by using a transfer gate circuit and CMOS technology, for example, a dynamic type latch circuit as shown in FIG. 3 and a static type latch circuit as shown in FIG. 4 have been used. The static latch circuit has an advantage of storing latch information as long as the power is on. On the other hand, in order to realize the static storage operation, the transfer gate TG2 of FIG. 4 is used to turn on and off between the output terminal QB and the terminal QQ, so that there is a drawback that the overall latch operation is slow.
In addition, the dynamic transfer gate latch circuit has the advantage that it uses a smaller number of transistors and can operate at a speed twice as fast as the static type. On the other hand, the memory holding function has a terminal QQ and a ground terminal G.
This is realized by the presence / absence of the charged electric charge of the capacitance Cm between the NDs, but this charged electric charge is volatilized by the leak current of the transistor, so that there is a drawback that the latch operation cannot be performed for a long time.

[0003]

Since the sequential circuit is conventionally based on the static type latch circuit or the dynamic type latch circuit as described above, the sequential circuit is not limited to the static type and dynamic type latch circuits. It had the above-mentioned drawbacks. It is an object of the present invention to provide a static transfer gate sequential circuit capable of high-speed operation equivalent to that of a dynamic type and capable of coping with low-speed operation.

[0004]

A latch circuit as a static type transfer gate sequential circuit for achieving the above object is, for example, as shown in a latch circuit SL in FIG. 1, one end of a transfer gate TG is connected to an input terminal D. And the other end of the transfer gate TG is connected to the input terminal of the inverter V1, the output terminal of the inverter V1 is connected to the output terminal QB and the input terminal of the inverter V2, and the output terminal of the inverter V2 is connected to the input terminal of the inverter V1. I decided to. In this case, the on resistance of the PMOS transistor forming the inverter V2 is further set to R
1. Transfer gate TG and preceding logic gate VL
, R2 is the series on-resistance between the output terminal and the ground terminal GND, and the logical threshold voltage of the inverter V1 is Vth.
When the power supply voltage is VD, the NMO has a relationship of (R2 / (R1 + R2)) × VD <Vth and constitutes the inverter V2.
When the on-resistance of the S transistor is R3 and the serial on-resistance between the transfer gate TG and the output terminal of the preceding logic gate VL and the power supply voltage terminal VDD is R4, (R3 / (R3 + R4)) × VD> Vth If there is a relationship, certainty of the latch operation can be obtained.

Alternatively, in a static transfer gate sequential circuit having a frequency dividing function for achieving the above object, for example, as shown in FIG. 5, the output terminal of the latch circuit SL1 is latched to the input terminal of the latch circuit SL2. Circuit S
The output terminal of L2 is connected to the input terminal of the inverter V3, and the output terminal of the inverter V3 is connected to the input terminal and the output terminal QQ of the latch circuit SL1.

Further, a static transfer gate sequential circuit having a prescaler function for achieving the above object is a 2-input NAND as shown in FIG.
The output terminal of the circuit ND to the input terminal of the latch circuit SL3,
The output terminal of the latch circuit SL3 is connected to the input terminal of the latch circuit SL4, and the output terminal of the latch circuit SL4 is connected to the first input terminal of the 2-input NAND circuit ND and the OR circuit O.
R is connected to the first input terminal, the output terminal of the OR circuit is connected to the input terminal of the latch circuit SL5, the output terminal of the latch circuit SL5 is connected to the input terminal of the latch circuit SL6,
The output terminal of the latch circuit SL6 is a 2-input NAND circuit ND
The second input terminal of the OR circuit OR is connected to the input terminal M, and the output terminal of the latch circuit SL4 is connected to the output terminal QQ.

Alternatively, in a static transfer gate sequential circuit having a function of dividing by half to achieve the above object, for example, as shown in FIG. 10, the output terminal of the latch circuit SL7 is connected to the input terminal of the latch circuit SL8. , The output terminal of the latch circuit SL8 is connected to the input terminal of the latch circuit SL9, the output terminal of the latch circuit SL9 is connected to the input terminal of the latch circuit SL10, and the output terminal of the latch circuit SL10 is connected to the input terminal of the latch circuit SL7. Then, the output terminal of the latch circuit SL8 is connected to the output terminal QQ, the output terminal of the latch circuit SL10 is connected to the output terminal QB, and further, between the output terminals of the latch circuits SL7 and SL9, between the output terminals of SL8 and SL10, and SL7. Between the output terminals of the transfer gates in each latch circuit of SL and SL9, SL8 and SL A set circuit RS for initially setting the voltage levels of the output terminals to mutually opposite levels between at least one pair of output terminals between the four output terminals of the transfer gates in each latch circuit of 0. Shall be connected.

[0008]

The sequential circuit of the present invention is based on the static type latch circuit of FIG. This latch circuit is shown in FIG.
The output of the conventional dynamic type latch circuit as shown in FIG. 2 has a configuration in which the circuit of the inverter V2 is added as described above or as shown in FIG. 1, and as will be described later, this addition is performed. The circuit provides the static type storage function to the dynamic type latch operation. Moreover, the inverter V2 in this case can be selected to be as small as possible, and the transfer gate TG can be changed like the conventional static type latch circuit.
Since it does not include 2, the additional circuit does not interfere with the high speed operation. That is, the present invention provides a high-speed sequential circuit which performs a static operation by adding a memory function to a high-speed dynamic sequential circuit and has an operation speed almost equal to that of the dynamic type. The conditions shown by the inequalities in the above means give the conditions necessary for surely performing the latch operation. Among the means of the present invention having the above-mentioned frequency dividing function, for example, the configuration shown in FIG. 10 has one fewer inverters in the critical path than the configuration shown in FIG. It becomes possible to further speed up.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a first embodiment of the present invention,
In (a), the circuit is described by logical symbols,
In (b), the circuit is described by a symbol using a MOS transistor. FIG. 2 is a timing chart of the input / output waveforms of FIG. In FIG. 1, SL is a static latch circuit of the present invention, TG is a transfer gate, V1 and V2.
Is an inverter, D is a data input terminal, QB is an output terminal,
CC is a clock signal input terminal, CB is a reverse phase clock signal input terminal, VDD is a power supply voltage terminal, GND is a ground terminal for grounding the circuit, and VL is an arbitrary logic gate added for explaining the present invention. .. Further, this circuit is characterized in that the on-resistance of the inverter V2 is large enough not to affect the logic result applied to the input terminal D. The circuit design conditions for designing this feature with a concrete CMOS circuit are described below. What is this condition?
The on-resistance of the PMOS transistor forming the inverter V2 is R1, the transfer gate TG and the CMO of the preceding stage are
Assuming that the series ON resistance between the output terminal of the S logic gate VL and the ground terminal GND is R2, the logic threshold voltage of the inverter V1 is Vth, and the power supply voltage is VD, (R2 / (R1 + R2)) × VD < NMO having a relationship of Vth (1) and configuring the inverter V2
When the on-resistance of the S transistor is R3 and the serial on-resistance between the transfer gate TG and the output terminal of the CMOS logic gate VL in the preceding stage and the power supply voltage terminal VDD is R4, (R3 / (R3 + R4)) × VD> Vth ( 2) to have the relationship. The necessity of such a condition will be described in detail below in the actual latch operation.
In FIG. 2, when the clock signal becomes high level at time t1, the transfer gate TG is turned on.
Therefore, the output of the CMOS logic gate VL passes through the terminal QQ, is input to the inverter V1, and is output as an inverted signal from the output terminal QB. Next, this signal passes through the inverter V2, and the original signal level is output to the terminal QQ. Next, when the clock voltage falls, the transfer gate TG is turned off, but because of the inverter V2, the potential of the terminal QQ is held in DC. From the output terminal QB, the signal when the clock falls is continuously held and output until t2 due to the data storage action of the inverters V1 and V2. This is the latch function itself. After that, at time t2 in FIG. 2, the signal at the output terminal QB is at the low level and the signal at the input terminal D is also at the low level. Immediately after the time t2, the transfer gate TG and the NMOS forming the CMOS logic gate
Turns on. In addition, P which constitutes the inverter V2
The MOS has been in the on state before the time t2. Therefore, the potential of the terminal QQ is the same as the PM constituting the inverter V2.
The on-resistance of the OS transistor is R1, the series on-resistance between the transfer gate TG and the output terminal of the CMOS logic gate VL of the preceding stage and the ground terminal GND is R2, the logic threshold voltage of the inverter V1 is Vth, and the power supply voltage is V.
Letting D be, V (QQ) = (R2 / (R1 + R2)) × VD (3). At this time, if V (QQ) <Vth (4), the inverter V1 starts the inversion operation, and the potential of the output terminal QB settles to the high level and the potential of the terminal QQ settles to the low level. However, if V (QQ)> Vth (5), the inverter V1 cannot perform the inversion operation, and therefore the potential of the output terminal QB is low level and the terminal QQ is low.
The potential of is also kept at the high level, and the latch signal cannot be rewritten. The above is the condition of the first expression.
It is obvious that the condition of the second equation is introduced because the opposite phenomenon occurs at the time t4. With such a configuration, the transfer gate type latch circuit to which the inverter V2 is added as in this patent performs a static operation. In the conventional dynamic latch circuit of FIG. 3, since the inverter V2 is not provided, there is no path for fixing the potential when the clock becomes low level.
Since the potential of is gradually changed, only a dynamic latch operation can be performed. This inverter V2
It is obvious that the smaller the above, the easier it is to satisfy the above conditions, the lighter the load on the CMOS logic gate VL, and the higher the operating speed of the latch circuit as a whole. The smaller the inverter V1, the lighter the load on the CMOS logic gate VL, but on the other hand, the drive capability to the next stage is reduced, and the operation speed of the entire latch circuit is reduced. Further, in the limit state in which the inverter V2 becomes gradually smaller and the parasitic capacitance component becomes negligibly smaller than the parasitic capacitance of the transfer gate TG, the operating speed becomes the operating speed of the dynamic latch circuit in FIG. It will also be clear that we are approaching. The lower limit of the size of the inverter V2 is that the current that overcomes the leakage current of the MOS transistor, which attempts to discharge the electric charge charged in the capacitance parasitic on the terminal QQ, is the inverter V2.
Can be supplied from the company. This current is on the order of picoamperes or less in the current state of the art of MOS transistor manufacturing technology. This leakage current is so small that it hardly needs to be considered as compared with that required in the circuit of the present invention, and as a practical matter, it is not necessary to consider the lower limit of the design of the inverter V2. It is desirable to make it as small as possible. If the above formula 1,
If the condition of the second expression is not satisfied, the latch signal cannot be rewritten. As a typical example thereof, there can be mentioned the case where the MOS transistors used for the transfer gate TG and the transistors used for the CMOS logic gate and the inverters V1 and V2 have exactly the same specifications. In such a case, the effect of the present invention cannot be realized. As a concrete means for making the ON resistance conform to the condition of the above equation, the simplest method is to change the width of the MOS transistor used. It is obvious that it can be realized by various means such as changing the threshold voltage. Further, a polysilicon FET or a thin film transistor (TFT), which is currently being tried in a CMOS memory or the like, can be used. In the above description, CMOS
Although the explanation has been made with only the inverter in mind, it has a high resistance due to a small NMOS and polysilicon, and a small PMO.
It is also possible to use an inverter or the like that combines S and high resistance. The transfer gate is also shown in Figure 1.
In addition to the CMOS type transfer gate as shown in (b), an NMOS transfer gate or a PMOS
It is obvious that the transfer gate alone can be used. It will be apparent that a similar circuit can be realized by using MESFET or the like instead of the MOS transistor.

FIG. 5 shows a second embodiment of the present invention, which is an example of the configuration of a 1/2 frequency divider realized by combining the static type latch circuits shown in the first embodiment. Here, SL1 and SL2 are static latch circuits, and V3 is a CMOS inverter. CC is a clock signal input terminal, CB is a reverse phase clock signal input terminal, and QQ is an output terminal for outputting a half frequency of the clock signal. Further, QQ1 and QQ2 respectively indicate internal terminals. FIG. 6 is a state table of each terminal of FIG. 5, and the voltage of each terminal changes to high (H) every time the clock input to this frequency divider changes. ) Or low (L). From this figure, it can be seen that a signal having a frequency twice that of the clock, that is, a frequency of 1/2 is output from the output terminal QQ. Like the latch circuit, this 1/2 frequency divider also has a built-in latch circuit in the latch circuits SL1 and SL2, which minimizes the inverter.
It is obvious that high-speed performance almost equal to that of the dynamic type 1/2 frequency divider shown in can be realized. In addition to the CMOS type transfer gate, the transfer gate may be an NMOS transfer gate or a PMOS.
It is obvious that the transfer gate alone can be used. It is also clear that if the NMOS transfer gate is SL1 and the PMOS transfer gate is SL2, a single-phase clock divider that inputs only the clock CC can be configured without using the anti-phase clock CB.

FIG. 8 shows a third embodiment of the present invention, which is a prescaler circuit. SL3, SL4, SL5, SL
6 is a static CMOS latch circuit, ND is CMO
S2 input NAND circuit, OR is CMOS2 input OR circuit, QQ is output terminal, M is input terminal, QQ3, QQ4,
QQ5 and QQ6 are internal terminals.

FIG. 9 is a state table of each terminal of FIG. 8. When the input signal M is at low level, the voltage of each terminal changes every time the clock input to this prescaler circuit changes.
It indicates whether it becomes a high level (H) or a low level (L). From this figure, it can be seen that a signal having a frequency three times as long as that of the clock, that is, a frequency of one third is output from the output terminal QQ. When the input signal M is at high level, the output of the OR circuit OR is always fixed to low, so this prescaler circuit is equivalent to the 1/2 frequency divider of FIG. Obviously, if this prescaler is designed under the same conditions as the latch circuit, it is possible to achieve high-speed performance that is almost the same as that of the dynamic type.

FIG. 10 shows a fourth embodiment of the present invention,
It is a 1/2 frequency divider. SL7, SL8, SL9, SL
10 is a static CMOS latch circuit, QQ is an output terminal, QQ7, QQ8, QQ9, and QQ10 are internal terminals,
CC is a clock input terminal, and CB is a reverse phase clock input terminal. RS is a set circuit for setting the initial state of the voltage of these internal terminals. With this set circuit, the internal terminal pair QQ7 and QQ9 or QQ8 and Q
Q10 needs to be set to the opposite level. Alternatively, the output terminal pair of SL7 and SL9 and the output terminal pair of SL8 and SL10 also need to be at opposite logic levels between the terminals of each terminal pair. The set circuit initializes the voltage for a pair or more pairs. In this case, if the set circuit is connected to the plurality of terminal pairs, the stability of the circuit and the convergence after setting can be improved.

A specific example of the set circuit is, for example, Q.
The drain of the NMOS transistor is connected to Q9, the source is connected to the GND terminal, and the high level signal of the set pulse is input to the gate. In addition, the terminal QQ7 has a PMOS
The drain of the transistor is connected, the source is connected to the VDD terminal, and the inverted signal (low level) of the set pulse is input to the gate. This enables the above set.

FIG. 11 is a timing chart of the input / output waveforms of FIG. 10, and the voltage of each terminal becomes high level (H) or low level (L) every time the input clock changes.
It is a state diagram showing whether or not. 2 of the clock from this figure
It can be seen that a signal having a doubled cycle, that is, a frequency of 1/2 is output from the output terminal QQ. The fourth embodiment is the same static half-divider as the second embodiment. In comparison with the second embodiment, the fourth embodiment requires about twice the number of transistors and power consumption, but has the characteristic that the maximum operating frequency is about twice as high. The reason for the high speed is that in the circuit of the second embodiment, the operation speed is controlled most by the latch circuit SL2 and the inverter V3.
In the circuit of the fourth embodiment, all the latch circuits SL7, SL8,
This is because it is time for the signal to propagate through either SL9 or SL10. That is, the speed of the fourth embodiment is increased by the time difference, that is, the time for the signal to propagate through the inverter V3. As described above, the second embodiment has high speed, but is characterized by low power consumption, and the fourth embodiment is characterized by higher speed operation. Besides, it is obvious that various sequential circuits such as a static D-type flip-flop and a shift register can be realized by combining the above-mentioned latch circuit, frequency divider, and prescaler.

[0016]

As described above, according to the present invention,
It is possible to realize a static type sequential circuit having an operation speed almost equal to that of a high speed dynamic type.

[Brief description of drawings]

FIG. 1 is a static type latch circuit according to a first embodiment of the present invention. (A) is described by a schematic symbol,
(B) is a description of the latch circuit of the present invention using a transistor.

FIG. 2 is a timing chart of input / output waveforms of the latch circuit of FIG.

FIG. 3 is a conventional dynamic latch circuit diagram. (A) is described by a circuit diagram symbol, (b) is a circuit description using a transistor.

FIG. 4 is a conventional static type latch circuit diagram.

FIG. 5 is a static half-divider diagram of the second embodiment of the present invention.

6 is a state table diagram of each terminal in FIG.

FIG. 7 is a diagram of a conventional dynamic half-divider.

FIG. 8 is a half / one-third prescaler diagram of the static type according to the third embodiment of the present invention.

9 is a state table diagram of each terminal of FIG.

FIG. 10 is a static half-divider diagram of the fourth embodiment of the present invention. It is described by the schematic symbol.

11 is a timing chart of input / output waveforms of FIG.

[Explanation of symbols]

D ... Data input terminal QB ... Latched data output terminal CC ... Clock signal input terminal CB ... Opposite phase clock signal input terminal VDD ... Power supply voltage terminal GND ... Ground terminal for circuit Cm ... Parasitic capacitance V1 to V3 ... CMOS inverters TG, TG1, TG2 ... CMOS transfer gates VL ... CMOS logic gates SL1 to SL10 ... Static type latch circuits QQ ... Output terminals for outputting a half frequency of a clock signal QB ... Outputs for outputting inverted signals of QQ Terminals QQ1 to QQ10 ... Internal terminal M ... Input terminal for switching 1/2 division, 1/3 division OR ... OR logic circuit ND ... 2-input NAND logic circuit RS ... Set circuit

Claims (5)

[Claims] 1. A static transfer gate sequential circuit as a latch circuit which is connected to the output of a logic gate VL and latches the output of the logic gate by inputting a clock, comprising a transfer gate TG and two inverters V1.
V2, input terminal D, output terminal QB, power supply voltage terminal VD
D, a ground terminal GND for grounding the circuit, and a clock input terminal CC. One end of the transfer gate TG is connected to the input terminal D, and the other end of the transfer gate TG is connected to the input terminal of the inverter V1 and the output of the inverter V1. Connect the output terminal QB and the input terminal of the inverter V2 to the inverter V2.
Of the static transfer gate sequential circuit, characterized in that the output terminals of the above are respectively connected to the input terminals of the inverter V1. 2. The inverter V according to claim 1, further comprising:
R1 is the on resistance of the PMOS transistor forming
The series ON resistance between the transfer gate TG and the output terminal of the preceding logic gate VL and the ground terminal GND is R.
2. When the logical threshold voltage of the inverter V1 is Vth and the power supply voltage is VD, there is a relationship of (R2 / (R1 + R2)) × VD <Vth, and the on-resistance of the NMOS transistor forming the inverter V2. Let R3 be R3, and let R4 be the series ON resistance between the output terminal of the transfer gate TG and the logic gate VL of the preceding stage and the power supply voltage terminal VDD, then the relationship of (R3 / (R3 + R4)) × VD> Vth should be satisfied. Characteristic static transfer gate sequential circuit. 3. The static transfer gate sequential circuit according to claim 1 or 2, which has latch circuits SL1 and SL2 as a sequential circuit, one inverter V3, and an output terminal QQ, and which has an output terminal of the latch circuit SL1. The output terminal of the latch circuit SL2 is connected to the input terminal of the latch circuit SL2 by the inverter V3.
A static transfer gate sequential circuit having a frequency dividing function, wherein the output terminal of the inverter V3 is connected to the input terminal of the latch circuit SL1 and the output terminal QQ. 4. A latch circuit SL3, SL4, SL5, SL6 as a static transfer gate sequential circuit according to claim 1 or 2, and one 2-input N.
It has an AND circuit ND, one 2-input OR circuit OR, an output terminal QQ, and an input terminal M, and the output terminal of the 2-input NAND circuit ND is connected to the latch circuit SL3.
To the input terminal of the latch circuit SL3, and the output terminal of the latch circuit SL4 is connected to the input terminal of the latch circuit SL4.
Connected to the first input terminal of the OR circuit OR and the output terminal of the OR circuit to the input terminal of the latch circuit SL5,
The output terminal of the latch circuit SL5 is connected to the input terminal of the latch circuit SL6, and the output terminal of the latch circuit SL6 is connected to the 2-input NAND circuit ND.
Of the OR circuit OR, the input terminal M is connected to the second input terminal of the OR circuit OR, and the output terminal QQ is connected to the output terminal of the latch circuit SL4. Transfer gate sequential circuit. 5. A latch circuit SL7, SL8, SL9, SL10 as a static transfer gate sequential circuit according to claim 1 or 2, and an output terminal of the latch circuit or an output terminal of a transfer gate in the latch circuit. Has a set circuit RS for setting the initial voltage level of the latch circuit and output terminals QQ and QB. The output terminal of the latch circuit SL7 is the input terminal of the latch circuit SL8, and the output terminal of the latch circuit SL8 is the latch circuit SL8.
9, the output terminal of the latch circuit SL9 is connected to the input terminal of the latch circuit SL10, the output terminal of the latch circuit SL10 is connected to the input terminal of the latch circuit SL7, and the output terminal of the latch circuit SL8 is connected to the above. The output terminal QQ is connected to the output terminal of the latch circuit SL10, and the output terminal QB is connected to the output terminals of the latch circuits SL7 and SL9.
10 output terminals, between output terminals of transfer gates in each latch circuit of SL7 and SL9, SL8 and SL
A set circuit RS for initializing the voltage levels of the output terminals between at least one pair of output terminals between four output terminals of the transfer gates in each of the latch circuits of 10 at mutually opposite levels. And a static transfer gate sequential circuit having a ½ frequency dividing function.