JPH05128043A - Data transfer control system - Google Patents

Abstract

PURPOSE:To shorten a transfer time by informing the total value of plural address areas only with one command and successively setting up the address values and sizes of these address areas. CONSTITUTION:The total value of the data sizes of data blocks A, B stored in a main memory 13 is sent to a peripheral device 12 by a command packet. The device 1 extracts the total value from the packet and stores the extracted value in size registers 42, 45. A CPU 25 in a host computer prepares a transfer control table 28 and sets up the leading address of the data block A in an address register 31 in accordance with the contents of the table 28. The host computer 11 sets up the data size of the block A in a size register 32 and starts up a DMA. Thus the data of the block A can be transferred to the device 12. The CPU 25 similarly transfers also the data block B to the device 12. A DMA control circuit 24 in the device 12 terminates the transfer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer control system for controlling data transfer between a host computer and peripheral devices.

[0002]

2. Description of the Related Art In a general computer system, an external storage device such as a magnetic tape device or a magnetic disk device is provided, and data is transferred between a host computer and these devices. When performing such data transfer, the CPU on the host computer side
Issues a data transfer command for each data to be transferred,
Transfer is performed by a series of operations based on this command.

FIG. 5 is for explaining a conventional data transfer control method. As shown in this figure, here, the main memory 1 provided on the host computer 11 is used.
Consider a case where the data blocks A and B in the areas separated from each other on 3 are transferred to the peripheral device 12. In this case, the CPU (not shown) first sends the first write command 14 to the peripheral device 12, and the data block A is sent to the peripheral device 12 by this command. When this is done,
The completion message 15 is returned from the peripheral device 12. The CPU then transfers the data block B to the peripheral device 12 by sending a second write command 16. Again, the peripheral device 12 returns the completion message 17 as well. As described above, in the conventional data transfer method, when transferring data existing in non-contiguous address areas on the main memory to the peripheral device, a write command is issued for each data block and the data is transferred in a predetermined sequence. It was supposed to transfer.

[0004]

As described above, in the conventional data transfer control system, when data of a plurality of areas which are not adjacent to each other in the linear address space of the host computer are transferred to the peripheral device, these areas are not transferred. It was necessary to issue as many transfer commands as the number of. Therefore, conventionally, there have been the following problems.

(1) A command must be issued for each distributed data block, and the overhead for controlling the command becomes large and the transfer time as a whole becomes long. That is, as shown in FIG. 8A, the time required to transfer the data block A is the sum of the transfer time of the first transfer command 14, the data block A, and the completion message 15 and these intervals. The time required to transfer the data block B is T1 and the time required to transfer the second transfer command 16, the data block B, and the completion message 17 and the interval between them is T2. Furthermore, a predetermined time interval T3 is also required between these two commands. Therefore, in the conventional data transfer control method, the time required to transfer the two data blocks A and B is T1 + T2 + T3, which requires a long time.

(2) There is a problem that the response of the peripheral device to the data transfer is delayed. For example, as shown in FIG. 6, when a magnetic tape device is considered as a peripheral device, operating system (OS) management data 19 and user data 20 are adjacent to each other on the magnetic tape 18 running in the direction of arrow 21. Then need to be recorded. However, the management data 19 of the OS is, for example, the main memory 1
3 (FIG. 5) at the position of the data block A, and the user data 20 at the position of the data block B (FIG. 5), what is the transfer of the OS management data 19 and the user data 20? Since each is executed by a separate command, between both recording areas on the magnetic tape 18,
A blank 29 as shown in FIG. 7 will be inserted. Therefore, in order to prevent such blank insertion, the magnetic tape device side needs a mechanical operation for aligning the data write head with a desired block for each data transfer command, and the processing time is extremely long. Become. Also, if the peripheral device is a hard disk or an optical disk device, these devices can transfer data continuously without waiting for rotation with a single data transfer command, but the multiple commands as described above are used. In the case of performing data transfer by, the rotation waiting time is required for each command, and the processing time becomes long.

The present invention has been made to solve the above problems, and it is possible to transfer data existing in a plurality of areas on a main memory of one device in a distributed manner to the other device in a short time. The purpose is to obtain a data transfer control method.

[0008]

A data transfer control system according to the present invention is a data transfer control system performed between a plurality of address areas which are not adjacent to each other on a main memory of a host computer and a peripheral device. On the host computer side, the total value of the area sizes of a plurality of address areas related to the data transfer on the main memory is notified to the peripheral device by one command, and a plurality of values are registered in the transfer address specifying register and the transfer size specifying register. By sequentially setting the start address value and the size of each of the address areas, the data is continuously transferred between the plurality of address areas and the peripheral device, and the peripheral device notifies the area notified by the host computer. The total size is stored, and the total size of data that is continuously transferred to and from the host computer is stored. When it reaches the sum of the size, it is obtained so as to terminate the transfer process.

[0009]

In the data transfer control system according to the present invention, the host computer notifies the peripheral device of the total value of a plurality of address areas related to the transfer on the main memory by one command, and the address value and the size of each address area. By sequentially setting and, data can be continuously transferred between these dispersed areas and the peripheral device. And when the transfer of the planned amount of data is completed,
The peripheral device sends a data transfer completion notification to the host computer.

[0010]

EXAMPLES The present invention will be described in detail below with reference to examples.

FIG. 1 shows a system to which a data transfer control system according to an embodiment of the present invention is applied.
As shown in the figure, the host computer 11 and the peripheral device 12 are provided with DMA control circuits 23 and 24, respectively, and are connected to each other via interface circuits 27 and 29. These DMA control circuits 23, 24
The data transfer control between the main memory 13 and the magnetic tape device 26 is performed according to the instructions of the CPUs 25 and 35 provided in each. Here, it is assumed that there are two data blocks A and B in the non-adjacent area of the main memory 13 of the host computer 11, and these are transferred to the peripheral device 12.

In a predetermined area on the main memory 13, a transfer control table 2 created prior to the start of data transfer.
8 (FIG. 2: to be described later) is stored. CP
According to the contents of this transfer control table 28, U25
The DMA control circuit 23 is controlled.

The DMA control circuit 23 is provided with the following registers.

(I) Address register 31: This register stores the start address of the data block A or B to be transferred prior to data transfer.

(Ii) Size register 32: This register stores the data size of each data block to be transferred.

Further, the interface circuit 27 is provided with the following various registers.

(I) Command register 33: This register stores a command given from the CPU 25.

(Ii) Status register 34: This register stores the contents of the status sent from the peripheral device 12.

(Iii) Size register 35: This register stores the same contents as the size register 32.

(Iv) Interrupt status register 36: The status from the peripheral device 12 that caused the external interrupt is stored. The contents of this register are the interface circuit 2
CPU 2 in response to external interrupt 37 from CPU 7 to CPU 25
5 is read.

On the other hand, on the side of the peripheral device 12, the data transferred to the interface circuit 29 is transferred to the MT drive circuit 30 under the control of the DMA control circuit 24 and recorded on the magnetic tape device 26. ing. DMA
The control circuit 24 is provided with the following registers.

(I) Address register 41: This register stores the address of the transfer destination extracted from the command packet from the host computer prior to data transfer. When the peripheral device is a magnetic tape device, it is a block address on the magnetic tape, and when the peripheral device 12 is a magnetic disk device, it is a sector address.

(Ii) Size register 42: As will be described later, this register stores the total transfer data size extracted from the command packet sent from the host computer 11.

Further, the interface circuit 29 is provided with the following various registers.

(I) Command register 43: This register stores the command contents extracted from the command packet sent from the host computer 11.

(Ii) Status register 44: The contents of the status sent to the host computer 11 are stored in this register.

(Iii) Size register 45: This register stores the same contents as the size register 42.

(Iv) Interrupt status register 46: The status from the host computer 11 that caused the external interrupt is stored. The contents of this register are read by the CPU 35 in response to an external interrupt 47 from the interface circuit 29 to the CPU 35.

The data transfer operation in the computer system having the above configuration will be described with reference to FIG. First, on the host computer side, when there is a request from the OS (step S101), the CPU 25 causes the transfer control table 28 including the transfer destination table 51 and the transfer source table 52 to be stored in the main memory 13 in a predetermined manner as shown in FIG. Create in the area. As shown in this figure, the transfer source table 5
1 includes a start address 54 of a block on the magnetic tape which is the transfer destination, a total transfer data size 55, and a transfer direction 56. The transfer source table 52 includes an entry 57 of the data block A, an entry 58 of the data block B, and an end mark 59. The entry 57 includes a start address 61 of the data block A on the main memory 13, a size 62, and a transfer direction 6.
It consists of 3. Similarly, the entry 58 has a start address 6 in the main memory 13 of the data block B.
4, size 65, and transfer direction 66. Here, the size of each of the data blocks A and B is 4
Bytes and 3 bytes will be described. The transfer direction represents data reading or data writing.

Now, C which has created the transfer control table 28
The PU 25 reads the contents of the transfer destination table 51 in the transfer control table 28 and sends the contents to the interface circuit 27, and sets the write command in the command register 33 (step S103). Then, the interface circuit 27 sends a command packet as shown in FIG. 3 to the peripheral device 12 (step S104).
As shown in the figure, this command packet is composed of the transfer destination block address 67, the total size 68 of the data blocks A and B, and the command content 69. Here, the total size of the data blocks A and B is 7 bytes.

Interface circuit 29 of peripheral device 12
However, when the command packet sent is received, CP
U35 has a total size of 68 (7 bytes here)
Is extracted and set in the size register 45 and the size register 42 of the DMA control circuit 24 (step S105).
At the same time, the command content 69 is set in the command register 43. Further, the CPU 35 extracts the block address 67 from the command packet, and the address register 4
It is set to 1 (step S106).

When such a receiving operation is completed, the CPU
The reference numeral 35 sends a data transfer request to the host computer 11 via the interface circuit 29, and the DM
The A control circuit 24 is activated (step S107). The interface circuit 27 of the host computer 11, which has received the data transfer request, stores the "data transfer request" in the interrupt status register 36 and sends the external interrupt signal 37 to the CPU 25 (step S129). C
The PU 25 refers to the interrupt status register 36, recognizes that the cause of the interrupt is due to the data transfer request, and then first reads the data from the transfer source table 52 of the transfer control table 28 (FIG. 2) on the main memory 13. Block A
The content of the entry 57 is read (step S10
9) and transfers it to the DMA control circuit 23 (step S110). As a result, the size “4 bytes” of the data block A is set in the size register 32 of the DMA control circuit 23 (step S111), and the start address of the data block A is set in the address register 31 (step S112). ). At this time, the size “4 bytes” of the data block A is also set in the size register 35 of the interface circuit 27.

Next, the CPU 25 activates the DMA control circuit 23 (step S113). Receiving this, the DMA control circuit 23 reads out 4 bytes of the content of the data block A in the main memory 13, and the peripheral device 12 reads the contents one byte at a time.
(Step S114). At this time, data transfer is performed between the interface circuits 27 and 29 by the following handshake for each byte. That is, the request (R
In response to the EQ signal, the interface circuit 27 transfers 1 byte of data and further acknowledges (ACK).
Send a signal. By repeating this, 4-byte data is transferred.

The DMA control circuit 24 on the side of the peripheral device 12 temporarily stores the sent 4-byte data in a buffer (not shown) and then sequentially writes it in the magnetic tape device 26 (step S115). Host computer 1
When the 4-byte data block A has been sent, the 1-side DMA control circuit 23 issues an internal DMA end interrupt to the CPU 25 (step S116).

Upon receiving this, the CPU 25 transfers the transfer source table 52 in the transfer control table 28 on the main memory 13.
The contents of the entry 58 of the data block B are read from (step S117) and transferred to the DMA control circuit 23 (step S118). As a result, the size "3 bytes" of the data block B is set in the size register of the DMA control circuit 23 (step S11).
9), the start address of the data block B is set in the address register 31 (step S120).

Next, the CPU 25 activates the DMA control circuit 23 (step S121). In response to this, the DMA control circuit 23 receives the data block B on the main memory 13.
3 bytes of contents are read out, 1 byte at a time for peripheral device 1
2 (step S122). In this case as well, the transfer is performed by the same handshake as described above.

In the DMA control circuit 24 of the peripheral device 12,
The received 3-byte data is temporarily stored in a buffer (not shown) and then sequentially transferred to the magnetic tape device 26 (step S123). DM of host computer 11
The A control circuit 23 sends a DMA end internal interrupt signal 38 to the CPU after the transfer of 3 bytes of the contents of the data block B is completed.
25 (step S124).

On the other hand, the CPU 35 of the peripheral device 12 sets the reception result status indicating whether or not the data is normally received in the status register 44 after the reception of 3 bytes of the data block B (step S125). To the host computer side (step S12)
6).

The interface circuit 27 of the host computer 11 stores the contents of the reception result status sent from the peripheral device 12 in the status register 34 and sends the external interrupt signal 37 to the CPU 25 (step S127). ..

CPU 25 receiving this external interrupt signal 37
Refers to the interrupt status register 36 and recognizes that the status that caused the external interrupt was the "reception result status".

Subsequently, when the completion message is sent from the CPU 35 of the peripheral device 12 (step S128), the interface circuit 27 sends an external interrupt signal 37 to the CPU 25 (step S129). CPU 25
By referring to the interrupt status register 36, it is recognized that the cause of the interrupt is the reception of the completion message.

Then, the CPU 25 analyzes the status set in the status register 34 (step S130).

As described above, according to this embodiment, only the command packet in step S104 is sent from the host computer 11 to the peripheral device 12, and the data block A separated in the main memory 13 is separated. And B will be transferred continuously. Therefore, as shown in FIG. 8B, the total time required for data transfer is T4. As shown in this figure, the total time T4 required for data transfer is defined by the command packet 48, the completion message 49 at the end of all data transfer, the data transfer time of the data blocks A and B, and the interval between them. Compared to the method, it is significantly shortened. The degree of shortening becomes more remarkable as the number of data blocks increases. In this figure, time T5 is
The contents of the address register 31 and the size register 32 are
The time required to reset the contents of data block A to the contents of data block B
This is a time that can be ignored compared to the tape running speed of 6. Therefore, as shown in FIG. 6, the contents of the two data blocks are continuously and adjacently written on the magnetic tape.

In this embodiment, the case where the data is written from the host computer 11 to the peripheral device 12 has been described, but the sequence when the data is read from the peripheral device 12 and transferred to the host computer 11 is almost the same. In this case, the transfer destination table 51 of the transfer control table 28 and the transfer direction 5 of the transfer source table 52
“Data read” may be set as 6, 63 and 66. As a result, a data read command packet is transmitted, and data transfer is performed in the opposite direction to the data write operation. However, at this time, data is transferred between the interface circuits 27 and 29 by the following handshake for each byte. That is, the interface circuit 29 sends 1 byte of data to the bus and then sends the REQ signal. In response to this, the interface circuit 27 takes in the data and sends out an ACK signal. By repeating this, data of a predetermined byte is transferred.

[0045]

As described above, according to the present invention,
Since the data in a plurality of data areas can be continuously transferred by sending the command only once, the overhead of data transfer control can be reduced. Further, since there is no time lag between the data blocks to be transferred, it is possible to eliminate the need for a mechanical operation for aligning the data write head or the like with a desired block for each command and a rotation waiting operation on the peripheral device side. There is an effect that the processing time can be remarkably shortened.

[Brief description of drawings]

FIG. 1 is a block diagram showing a computer system to which a data transfer control system according to an embodiment of the present invention is applied.

FIG. 2 is an explanatory diagram showing the contents of a transfer control table created on a main memory.

FIG. 3 is an explanatory diagram showing a command packet sent from a host computer.

FIG. 4 is a sequence diagram for explaining a data transfer control method in the embodiment of the present invention.

FIG. 5 is an explanatory diagram for explaining a conventional data transfer control method.

FIG. 6 is an explanatory diagram showing an example of a data format on a magnetic tape device.

FIG. 7 is an explanatory diagram showing a state in which a blank is inserted between data blocks when writing to a magnetic tape.

FIG. 8 is an explanatory diagram comparing the time required by the conventional data transfer control method with the time required by the data transfer control method of the present invention when transferring a plurality of data blocks.

[Explanation of symbols]

 11 Host Computer 12 Peripheral Device 13 Main Memory 23, 24 DMA Control Circuit 25, 35 CPU 27, 29 Interface Circuit 28 Transfer Control Table 31, 41 Address Register 32, 42 Size Register 51 Transfer Source Table 52 Transfer Destination Table

Claims (1)

[Claims] 1. A control method of data transfer between a plurality of address areas on a main memory of a host computer, which are not adjacent to each other, and a peripheral device, wherein the host computer performs data transfer on the main memory. The total value of the area sizes of the plurality of related address areas is notified to the peripheral device by one command, and the start address value and the size of each of the plurality of address areas are stored in the transfer address specifying register and the transfer size specifying register. By sequentially setting, the data is continuously transferred between these address areas and the peripheral device, and the peripheral device side stores the total value of the region size notified from the host computer, and Transfer when the total size of data continuously transferred to and from the computer reaches the total value of the area size. The data transfer control method is characterized in that so as to end the management.