JPH0512852B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing an insulated gate (MIS) transistor, particularly an amorphous silicon MIS transistor, which prevents film burrs in the channel portion and reduces the operating current in the on state. The purpose is to provide a manufacturing method for obtaining highly reliable MIS transistors.

Amorphous silicon, which is formed by containing a few percent of hydrogen or fluorine in its composition to compensate for imperfections in atomic bonding pairs, can be formed at low temperatures and can be made into large areas. For these reasons, it is attracting attention as a material for realizing low-cost solar cells. However, compared to single crystal silicon, the free electron mobility is 0.1 to 1 cm ² /V-sec, which is more than two orders of magnitude smaller, making it impossible to obtain a semiconductor device with performance worthy of integration.
Even so, it is possible to obtain a switching array of MIS transistors that constitute an image display device by combining them with, for example, a liquid crystal cell that does not require high-speed operation or a large on-current.

FIGS. 1 and 2 are a plan view of an amorphous silicon MIS transistor developed to achieve the above object, and a sectional view of the manufacturing process taken along line A-A'. First, as shown in FIG. 2a, a first metal layer 2, which will become a gate electrode, is selectively deposited on an insulating substrate, for example, a glass plate 1. As shown in FIG. Next, a gate insulating layer 3 made of silicon nitride, for example, a first amorphous silicon layer 4 containing almost no impurity as a donor or acceptor, and a second amorphous silicon layer 4 containing a large amount of the impurity, for example phosphorus or boron, are formed on the entire surface. A silicon layer 5 is applied. Plasma deposition using glow discharge of silane gas is a simple method for depositing these thin films.
If silicon nitride is to be obtained for the gate insulating layer 3, ammonia may be added to the preparation gas, and if amorphous silicon containing impurities is to be obtained, a gas such as diborane or phosphine may be added to the preparation gas.

Thereafter, as shown in FIG. 2b, the amorphous silicon layers 4 and 5 are selectively removed to form islands 4' and 5'. Although not shown, an opening 6 (shown in FIG. 1) is formed in the gate insulating layer 3 on the first metal layer 2 to expose a part of the first metal layer 2, and then the second metal layer 2 is exposed.
As shown in Figure c, source/drain wirings 7 and 8 made of a second metal layer partially overlapping the first metal layer 2 serving as the gate electrode are selectively formed to avoid an offset gate structure. be done. At this time, a gate wiring 9 (shown in FIG. 1) that contacts the gate electrode through the opening 6 is also formed. Finally, as shown in Figure 2d, source/drain wiring 7, 8
Using this as a mask, the amorphous silicon layer 5' containing impurities is selectively removed to complete an amorphous silicon MIS transistor with a conventional structure.

The impurity-containing amorphous silicon layers 10 and 11 interposed between the source/drain wirings 7 and 8 and the amorphous silicon layer 4' are necessary to form a good ohmic contact, and their existence Although it is possible to operate as an MIS transistor without it, the operating voltage tends to be high, so in that case, consideration must be given to the material and deposition method of the source-drain wirings 7 and 8. If the amorphous silicon layers 10 and 11 containing impurities are present, common aluminum is sufficient for the source/drain wirings 7 and 8.

Now, as shown in FIG. 2d, the amorphous silicon layer 5' containing impurities is connected to the source/drain wiring 7,
8 as a mask, but if the removal is insufficient, the source/drain 1
It is clear that the conductive amorphous silicon layer containing residual impurities between 0 and 11 becomes electrically conductive, increasing the leakage current between the source and drain. However, there is no etching material that has a large selectivity ratio between an amorphous silicon layer containing impurities and an amorphous silicon layer that does not contain impurities, in other words, a large etching rate ratio. :Nitric acid=1:30 Even if an appropriate amount of acetic acid is added to the solution, the selection ratio is about 5 at most. In other words, it is extremely difficult to selectively remove only the amorphous silicon layer containing impurities.

Therefore, as shown in FIG. 2d, when the amorphous silicon layer 5' containing impurities is removed, the amorphous silicon layer 4' not containing impurities is usually
Generally, a portion of the groove is removed to form a concave shape 12. As a result, although an increase in leakage current can be suppressed, the thickness of the impurity-free amorphous silicon layer 4' constituting the channel of the MIS transistor is definitely reduced. In a particular combination, molybdenum is used for the gate metal layer 2, amorphous silicon layer 5' containing phosphorus as an impurity, aluminum is used for the source/drain/gate wirings 7, 8, and 9, and the etching liquid is hydrofluoric acid:nitric acid. When a 1:30 solution is used, the etching rate of amorphous silicon increases by about 5 to 10 times, and up to 5000 Å of impurity-free amorphous silicon layer 4' disappears in just a few seconds. This is an electrochemical reaction that occurs only when the gate electrode 2 is connected to the gate wiring 9 through the opening 6.

If the impurity-free amorphous silicon layer 4' constituting the channel portion becomes too thin due to such development, the on-current of the MIS transistor will decrease significantly, and may even become less than 1/10 of that in the case of proper etching. Not rare. A further disadvantage is that in the conventional structure example shown in FIG. 2d, the opposite side of the channel is exposed to the outside air, and therefore moisture in the air is likely to be adsorbed. Since the OH ^- groups in the adsorbed moisture change the channel portion to the P-type, the threshold voltage of the MIS transistor in n-channel operation begins to increase as soon as moisture adsorption begins, and converges to a certain value. However, about
It has been found that heat treatment in dry nitrogen gas at 150° C. causes the adsorbed moisture to be lost and the properties immediately after manufacture are restored, but such heat treatment is necessary.

As described above, in amorphous silicon MIS transistors with conventional structures, unevenness in characteristics due to film burrs in the channel region cannot be avoided, and in addition, reliability is extremely unstable. The present invention has been developed in view of the above circumstances, and its gist is the introduction of an insulating layer that insulates the channel portion from the outside air.Examples of the present invention will be described below with reference to FIGS. 3 and 4. In FIGS. 3 and 4, parts having the same functions are given the same numbers as in FIGS. 1 and 2.

First, as shown in FIG. 4a, a gate metal layer 2 made of, for example, chromium or molybdenum is placed on an insulating substrate 1.
is selectively deposited and formed. Next, a first insulating layer 3 made of, for example, silicon nitride, an amorphous silicon layer 4 containing no impurities to serve as a donor or acceptor, and a second insulating layer 13 made of, for example, silicon nitride are sequentially deposited on the entire surface. These thin films are deposited in the same chamber, preferably in a deposition apparatus having a vacuum conveyance path and multiple chambers, so that they are not exposed to the atmosphere after each deposition. In this sense, plasma deposition by glow discharge of silane-based gas is advantageous. Thereafter, a molybdenum layer 14 having a thickness of, for example, 5000 Å is deposited over the entire surface.

As shown in FIG. 4b, the molybdenum layer 14 and part of the second insulating layer 13 are left as 14' and 13', which are smaller than the gate metal layer 2, and an amorphous silicon layer 4 containing no impurities is selected. to be exposed. Then, for example, an amorphous silicon layer 5 containing impurities is formed on the entire surface.
Molybdenum layer 1 when deposited with a thickness of 500 to 1000 Å
Since the layer 4' is as thick as 5000 Å, the amorphous silicon layer 5 easily breaks at the step portion 15 of the laminated portion of the molybdenum layer 14' and the second insulating layer 13'.
Therefore, the molybdenum layer 14' was removed in nitric acid or hydrogen peroxide water, and the amorphous silicon layer containing impurities on the molybdenum layer 14' was removed, and the second insulating layer 13' was polished as shown in FIG. 4c. An amorphous silicon layer 5 containing impurities and an amorphous silicon layer 4 containing no impurities are formed in an island shape 5',
4'.

Although not shown, the first layer on the gate metal layer 2
After forming an opening 6 (shown in FIG. 3) in the insulating layer 3 of FIG. 8 is formed to complete the MIS transistor according to the present invention. Of course, the gate wiring 9 is also formed at the same time.

As mentioned above, in FIG.
Furthermore, in this process, the gate metal layer 2 is formed by a so-called lift-off process that removes the impurity-free amorphous silicon layer 4 and the first insulating layer 3, both electrically and chemically. Since they are separated, a MIS transistor can be obtained regardless of the material of the gate metal layer 2, and there is no fear that the impurity-free amorphous silicon layer 4' constituting the channel portion will deteriorate. Therefore, there is no variation in transistor characteristics. Furthermore, since the second insulating layer 13' shields the channel section from the atmosphere, even if moisture in the air is adsorbed to the second insulating layer 13', the channel section will not become p-type. The device operates stably without any fluctuation in threshold voltage during operation or storage.

Of course, reliability can be expected to be improved by passivation in a general sense, that is, by depositing an appropriate insulating layer on the entire surface after the process shown in FIG. ,8,
Since the passivation insulating layer is deposited in the presence of 9, the passivation insulating layer is likely to be contaminated with the wiring metal and impurities contained in the wiring metal. Further, depending on the combination of materials, chemical reactions between the passivation insulating layer and the wiring metal may cause unnecessary troubles such as increased resistance of the wiring metal or increased leakage between wirings. On the other hand, in the present invention, the second insulating layer 13 having a passivation function is formed subsequent to the deposition of the amorphous silicon layer 4 which does not contain impurities. The interface with the insulating layer 13 and the second insulating layer 13 itself have high purity on a semiconductor level, and the introduction of the second insulating layer 13, which is also a passivation film, has the advantage that various characteristics of the MIS transistor do not change. The effect was obtained.

As is clear from the above explanation, the present invention can be applied to all silicon semiconductors except single crystal silicon, and can be applied to microcrystalline silicon and polycrystalline silicon in addition to amorphous silicon taken up in the examples. do not have. It goes without saying that, in addition to silicon nitride, silicon oxide, silicon carbide, aluminum oxide, or a mixture thereof may be appropriately used for the first and second insulating layers. In addition, although the case where the offset is avoided has been explained above, when creating the offset in order to increase the withstand voltage of the transistor, the width of the second insulating layer 13' is made wider than the width of the gate electrode 2 in FIG. You can also.

As described above, according to the present invention, the impurity-free amorphous silicon layer constituting the channel portion does not deteriorate, the transistor characteristics do not vary, and due to the presence of the second insulating layer, A transistor that can operate stably for a long time can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a schematic plan view showing the structure of a conventional MIS transistor, FIGS. 2 a to d are cross-sectional views of the manufacturing process taken along line A-A' of the transistor in FIG. 1, and FIG. 3 is an embodiment of the present invention. A schematic plan view of the MIS transistor according to the example, and FIGS. 4a to 4d are sectional views of the manufacturing process along the line A-A' of the transistor in FIG. 3. 1... Insulating substrate, 2... Gate metal layer, 3...
...First insulating layer, 4, 4'... Amorphous silicon layer not containing impurities, 5, 5'... Amorphous silicon layer containing impurities, 7, 8, 9... Source/drain gate Wiring, 10, 11... Source/drain, 13, 13'... Second insulating layer, 14, 1
4'...Molybdenum layer.

Claims (1)

[Claims] 1. A step of selectively forming a first metal layer to serve as a gate on an insulating substrate, and a step of forming a first insulating layer on the entire surface,
A step of continuously forming a first non-single-crystal semiconductor layer and a second insulating layer that are mainly composed of silicon and do not contain impurities that serve as donors or acceptors without being exposed to the atmosphere, and a step of forming molybdenum on the second insulating layer. After forming the layer, a step of selectively forming a laminated portion consisting of the molybdenum layer and a second insulating layer on the first non-single crystal semiconductor layer, and doping the entire surface with an impurity containing silicon as a main component and serving as a donor or acceptor. a step of forming a second non-single-crystalline semiconductor layer containing the molybdenum layer, and removing the molybdenum layer using nitric acid or hydrogen peroxide to form a second non-single-crystalline semiconductor layer on the molybdenum layer. a step of forming the second non-single crystal semiconductor layer and the first non-single crystal semiconductor layer into an island shape including the selectively left second insulating layer; selectively forming a second metal layer to be a source and a drain on the first insulating layer including a part of the second non-single crystal semiconductor layer formed in an island shape. A method for manufacturing a characteristic insulated gate transistor.